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    Memory system with error correction decoder architecture having reduced latency and increased throughput
    1.
    发明授权
    Memory system with error correction decoder architecture having reduced latency and increased throughput 有权
    具有纠错解码器架构的存储器系统具有降低的延迟和增加的吞吐量

    公开(公告)号：US08479085B2

    公开(公告)日：2013-07-02

    申请号：US12191458

    申请日：2008-08-14

    申请人： Nam Phil Jo ,  Jun Jin Kong ,  Chan Ho Yoon ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    发明人： Nam Phil Jo ,  Jun Jin Kong ,  Chan Ho Yoon ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1068 ,  G11C7/1006 ,  G11C2029/0411

    摘要： A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

    摘要翻译： 存储器系统包括：包括纠错解码器的存储器控​​制器。 纠错解码器包括：解复用器，适于接收数据并将数据解复用为第一组数据和第二组数据; 用于分别存储第一和第二组数据的第一和第二缓冲存储器; 误差检测器; 误差校正器 以及多路复用器，其适于多路复用第一组数据和第二组数据，并将复用的数据提供给误差校正器。 当误差校正器校正第一组数据中的错误时，误差检测器检测存储在第二缓冲存储器中的第二组数据中的错误。

    Error control code apparatuses and methods of using the same
    3.
    发明申请
    Error control code apparatuses and methods of using the same 有权
    错误控制代码设备及其使用方法

    公开(公告)号：US20080276149A1

    公开(公告)日：2008-11-06

    申请号：US11905733

    申请日：2007-10-03

    申请人： Jun Jin Kong ,  Seung-Hwan Song ,  Young Hwan Lee ,  Dong Hyuk Chae ,  Kyoung Lae Cho ,  Nam Phil Jo ,  Sung Chung Park ,  Dong Ku Kang

    发明人： Jun Jin Kong ,  Seung-Hwan Song ,  Young Hwan Lee ,  Dong Hyuk Chae ,  Kyoung Lae Cho ,  Nam Phil Jo ,  Sung Chung Park ,  Dong Ku Kang

    IPC分类号： G06F11/07

    CPC分类号： G06F11/1008

    摘要： An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.

    摘要翻译： 错误控制码（ECC）装置可以包括基于频道信息产生ECC控制信号的控制信号发生器。 ECC装置还可以包括：多个ECC编码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或编码单元，其使用从所述多个ECC编码控制器输出的多个数据，将输入数据编码为对应于所述ECC控制信号的多个子数据进行编码。 另外或者可选地，ECC装置可以包括：多个ECC解码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或解码单元，其使用从所述多个ECC解码控制器输出的多个数据将对应于所述ECC控制信号的多个解码输入数据解码为一条输出数据。

    Error control code apparatuses and methods of using the same
    5.
    发明授权
    Error control code apparatuses and methods of using the same 有权
    错误控制代码设备及其使用方法

    公开(公告)号：US08112693B2

    公开(公告)日：2012-02-07

    申请号：US11905734

    申请日：2007-10-03

    申请人： Jun Jin Kong ,  Seung-Hwan Song ,  Dong Hyuk Chae ,  Kyoung Lae Cho ,  Seung Jae Lee ,  Nam Phil Jo ,  Sung Chung Park ,  Dong Ku Kang

    发明人： Jun Jin Kong ,  Seung-Hwan Song ,  Dong Hyuk Chae ,  Kyoung Lae Cho ,  Seung Jae Lee ,  Nam Phil Jo ,  Sung Chung Park ,  Dong Ku Kang

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1072

    摘要： An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.

    摘要翻译： 应用于多电平单元（MLC）方法的存储器的错误控制码（ECC）装置可以包括：旁路控制信号发生器，其生成旁路控制信号; 以及ECC执行单元，其可以包括至少两个ECC解码块，基于旁路控制信号确定是否绕过所述至少两个ECC解码块的一部分，和/或执行ECC解码。 另外或在替代方案中，ECC执行单元可以包括至少两个ECC编码块，基于旁路控制信号确定是否绕过至少两个ECC编码块的一部分，和/或执行ECC编码。 还公开了应用于MLC方法的存储器的ECC方法和存储用于实现应用于MLC方法的存储器的EEC方法的程序的计算机可读记录介质。

    Apparatus and method for multi-bit programming
    6.
    发明申请
    Apparatus and method for multi-bit programming 审中-公开
    多位编程的装置和方法

    公开(公告)号：US20090046510A1

    公开(公告)日：2009-02-19

    申请号：US12007775

    申请日：2008-01-15

    申请人： Seung-Hwan Song ,  Jun Jin Kong ,  Sung Chung Park ,  Heeseok Eun ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    发明人： Seung-Hwan Song ,  Jun Jin Kong ,  Sung Chung Park ,  Heeseok Eun ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    IPC分类号： G11C7/10

    CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641

    摘要： Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus may include: a first programming unit that stores data corresponding to a number of first bits in at least one first memory cell that may be connected to at least one first bit line; and a second programming unit that stores data corresponding to a number of second bits in at least one second memory cell that may be connected to at least one second bit line. Through this, it may be possible to improve data reliability and increase a number of bits to be stored in the entire memory cell.

    摘要翻译： 提供了多位编程设备和方法。 一种多位编程设备可以包括：第一编程单元，其存储对应于可连接到至少一个第一位线的至少一个第一存储器单元中的多个第一位的数据; 以及第二编程单元，其将可能连接到至少一个第二位线的至少一个第二存储器单元中的与第二位数相对应的数据存储。 由此，可以提高数据可靠性并增加要存储在整个存储单元中的位数。

    Nonvolatile memory devices that utilize error correction estimates to increase reliability of error detection and correction operations
    7.
    发明授权
    Nonvolatile memory devices that utilize error correction estimates to increase reliability of error detection and correction operations 有权
    利用误差校正估计的非易失性存储器件增加错误检测和校正操作的可靠性

    公开(公告)号：US08239747B2

    公开(公告)日：2012-08-07

    申请号：US12216744

    申请日：2008-07-10

    申请人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

    发明人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1072 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152

    摘要： Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

    摘要翻译： 示例性实施例可以提供存储器件和存储器数据读取方法。 根据示例实施例的存储器件可以包括多位单元阵列，错误检测器，其可以从多位单元阵列中的存储器页读取第一数据页，并且可以检测第一数据页的错误位， 以及估计器，其可以识别存储错误位的多位单元，并且可以估计存储在所识别的多位单元中的数据在第二数据页的数据中。 因此，存储器件和存储器数据读取方法可以具有当读取存储在多位单元中的数据并且监视多位单元的状态而没有额外开销时减小误差的效果。

    Memory data detecting apparatus and method for controlling reference voltage based on error in stored data
    8.
    发明授权
    Memory data detecting apparatus and method for controlling reference voltage based on error in stored data 有权
    存储器数据检测装置和基于存储数据中的误差来控制参考电压的方法

    公开(公告)号：US07929346B2

    公开(公告)日：2011-04-19

    申请号：US12216745

    申请日：2008-07-10

    申请人： Dong Hun Yu ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Jae Hong Kim ,  Seung-Hwan Song

    发明人： Dong Hun Yu ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Jae Hong Kim ,  Seung-Hwan Song

    IPC分类号： G11C16/06 ,  G11C16/34 ,  G11C16/26

    CPC分类号： G11C7/1006 ,  G11C7/14 ,  G11C11/5642 ,  G11C29/00 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50 ,  G11C2211/5634

    摘要： Example embodiments may relate to a method and an apparatus for reading data stored in a memory, for example, providing a method and an apparatus for controlling a reference voltage based on an error of the stored data. Example embodiments may provide a memory data detecting apparatus including a first voltage comparator to compare a threshold voltage of a memory cell with a first reference voltage, a first data determiner to determine a value of at least one data bit stored in the memory cell according to a result of the comparison, an error verifier to verify whether an error occurs in the determined value, a reference voltage determiner to determine a second reference voltage that is lower than the first reference voltage based on a result of the verification, and a second data determiner to re-determine the value of the data based on the determined second reference voltage.

    摘要翻译： 示例性实施例可以涉及用于读取存储在存储器中的数据的方法和装置，例如提供一种基于存储的数据的错误来控制参考电压的方法和装置。 示例性实施例可以提供一种存储器数据检测装置，其包括用于将存储器单元的阈值电压与第一参考电压进行比较的第一电压比较器，第一数据确定器，用于根据存储器单元存储的至少一个数据位的值，根据 比较结果，用于验证所确定的值是否发生错误验证器，基于验证结果确定低于第一参考电压的第二参考电压的参考电压确定器，以及第二数据 确定器，以基于所确定的第二参考电压重新确定数据的值。

    Apparatus and method of multi-bit programming
    9.
    发明申请
    Apparatus and method of multi-bit programming 有权
    多位编程的装置和方法

    公开(公告)号：US20090103359A1

    公开(公告)日：2009-04-23

    申请号：US12073101

    申请日：2008-02-29

    申请人： Seung-Hwan SONG ,  Kyoung Lae Cho ,  Heeseok Eun ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Sung Chung Park

    发明人： Seung-Hwan SONG ,  Kyoung Lae Cho ,  Heeseok Eun ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Sung Chung Park

    IPC分类号： G11C16/06 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3418 ,  G11C2211/5621

    摘要： Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may comprise: a multi-bit cell array that includes a first multi-bit cell and a second multi-bit cell; a programming unit for programming first data in the first multi-bit cell, and programming second data in the second multi-bit cell; and a verification unit for verifying whether the first data is programmed in the first multi-bit cell using a first verification voltage, and verifying whether the second data is programmed in the second multi-bit cell using a second verification voltage. The multi-bit programming apparatus may generate better threshold voltage distributions in a multi-bit cell memory.

    摘要翻译： 提供了多位编程设备和/或方法。 多比特编程装置可以包括：包括第一多比特小区和第二多比特小区的多比特单元阵列; 编程单元，用于对第一多位单元中的第一数据进行编程，以及编程第二多位单元中的第二数据; 以及验证单元，用于使用第一验证电压来验证第一数据是否被编程在第一多位单元中，以及使用第二验证电压来验证第二数据是否被编程在第二多位单元中。 多比特编程装置可以在多比特单元存储器中产生更好的阈值电压分布。

    Memory devices and methods for determining data of bit layers based on detected error bits
    10.
    发明授权
    Memory devices and methods for determining data of bit layers based on detected error bits 有权
    用于基于检测到的错误位来确定位层的数据的存储器件和方法

    公开(公告)号：US07903459B2

    公开(公告)日：2011-03-08

    申请号：US12232150

    申请日：2008-09-11

    申请人： Donghun Yu ,  Kyoung Lae Cho ,  Dongku Kang ,  Dong Hyuk Chae ,  Jun Jin Kong

    发明人： Donghun Yu ,  Kyoung Lae Cho ,  Dongku Kang ,  Dong Hyuk Chae ,  Jun Jin Kong

    IPC分类号： G11C16/04

    CPC分类号： G11C16/26 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C29/00 ,  G11C2029/0411 ,  G11C2211/5621

    摘要： Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage intervals, a determination unit configured to determine data of a first bit layer based on the detected first threshold voltage intervals, and an error detection unit configured to detect an error bit of the data of the first bit layer. In this instance, the determination unit may determine data of a second bit layer using a second threshold voltage interval having a value of the first bit layer different from the detected error bit and being nearest to a threshold voltage of a multi-bit cell corresponding to the detected error bit.

    摘要翻译： 公开了一种存储器件和存储器数据读取方法。 存储器件可以包括多位单元阵列，阈值电压检测单元，被配置为从多个阈值电压间隔中检测包括多位单元阵列的多位单元的阈值电压的第一阈值电压间隔， 单元，被配置为基于检测到的第一阈值电压间隔来确定第一位层的数据;以及错误检测单元，被配置为检测第一位层的数据的错误位。 在这种情况下，确定单元可以使用具有与检测到的错误位不同的第一位层的值的第二阈值电压间隔来确定第二位层的数据，并且最接近对应于多个位单元的阈值电压 检测到错误位。