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公开(公告)号：US08254453B2
公开(公告)日：2012-08-28
申请号：US12690921
申请日：2010-01-20
申请人： Chan-Shih Lin , Shu-Hsien Chou , Kuei-Lan Lin
发明人： Chan-Shih Lin , Shu-Hsien Chou , Kuei-Lan Lin
CPC分类号： H04N19/42 , H04N19/12 , H04N19/44 , H04N19/46 , H04N19/593
摘要： A multi-format video decoder includes a bitstream buffer, a system controller, a bitstream decoding unit, an intra mode decoding unit and a shared prediction module. The system controller selectively generates a first control signal or a second control signal according to a video bitstream. The bitstream decoding unit generates a decoding information signal according to the video bitstream when receiving the first control signal. The intra mode decoding unit generates an intra mode signal when receiving the second control signal. The shared prediction module performs an AC/DC prediction upon a current block of the video bitstream to generate a current first prediction result according to the decoding information signal and performs an intra prediction upon the current block to generate a current second prediction result according to the intra mode signal. The shared prediction module includes shared components being utilized in the AC/DC prediction and the intra prediction.
摘要翻译： 多格式视频解码器包括比特流缓冲器，系统控制器，比特流解码单元，帧内模式解码单元和共享预测模块。 系统控制器根据视频比特流选择性地产生第一控制信号或第二控制信号。 比特流解码单元在接收到第一控制信号时根据视频比特流生成解码信息信号。 帧内模式解码单元在接收到第二控制信号时产生帧内模式信号。 共享预测模块对视频比特流的当前块执行AC / DC预测，根据解码信息信号产生当前第一预测结果，并根据当前块执行帧内预测，根据该预测结果生成当前第二预测结果 帧内模式信号。 共享预测模块包括在AC / DC预测和帧内预测中使用的共享组件。
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公开(公告)号：US20110176609A1
公开(公告)日：2011-07-21
申请号：US12690921
申请日：2010-01-20
申请人： Chan-Shih Lin , Shu-Hsien Chou , Kuei-Lan Lin
发明人： Chan-Shih Lin , Shu-Hsien Chou , Kuei-Lan Lin
CPC分类号： H04N19/42 , H04N19/12 , H04N19/44 , H04N19/46 , H04N19/593
摘要： A multi-format video decoder includes a bitstream buffer, a system controller, a bitstream decoding unit, an intra mode decoding unit and a shared prediction module. The system controller selectively generates a first control signal or a second control signal according to a video bitstream. The bitstream decoding unit generates a decoding information signal according to the video bitstream when receiving the first control signal. The intra mode decoding unit generates an intra mode signal when receiving the second control signal. The shared prediction module performs an AC/DC prediction upon a current block of the video bitstream to generate a current first prediction result according to the decoding information signal and performs an intra prediction upon the current block to generate a current second prediction result according to the intra mode signal. The shared prediction module includes shared components being utilized in the AC/DC prediction and the intra prediction.
摘要翻译： 多格式视频解码器包括比特流缓冲器，系统控制器，比特流解码单元，帧内模式解码单元和共享预测模块。 系统控制器根据视频比特流选择性地产生第一控制信号或第二控制信号。 比特流解码单元在接收到第一控制信号时根据视频比特流生成解码信息信号。 帧内模式解码单元在接收到第二控制信号时产生帧内模式信号。 共享预测模块对视频比特流的当前块执行AC / DC预测，根据解码信息信号产生当前第一预测结果，并根据当前块执行帧内预测，根据该预测结果生成当前第二预测结果 帧内模式信号。 共享预测模块包括在AC / DC预测和帧内预测中使用的共享组件。
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公开(公告)号：US20090228770A1
公开(公告)日：2009-09-10
申请号：US12042995
申请日：2008-03-05
申请人： Chan-Shih Lin , Kuei-Lan Lin
发明人： Chan-Shih Lin , Kuei-Lan Lin
IPC分类号： H03M13/03
摘要： A video decoder capable of generating a check data in response to a data selection code for debugging is disclosed. The video decoder includes a plurality of functional blocks, wherein each said plurality of functional blocks has a output signal to be used as an input signal for a next stage functional block; a multiplexer (209) that receives a plurality of data extracted from said plurality of output signals from said plurality of functional blocks, and outputs one of said plurality of data according to said data selection code; and a check logic (210) that generates said check data by calculating one of said plurality of data outputted from said multiplexer.
摘要翻译： 公开了能够响应用于调试的数据选择代码生成检查数据的视频解码器。 视频解码器包括多个功能块，其中每个所述多个功能块具有用作下一级功能块的输入信号的输出信号; 多路复用器（209），其从所述多个功能块接收从所述多个输出信号提取的多个数据，并根据所述数据选择码输出所述多个数据中的一个; 以及通过计算从所述多路复用器输出的所述多个数据中的一个产生所述校验数据的校验逻辑（210）。
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公开(公告)号：US08156410B2
公开(公告)日：2012-04-10
申请号：US12042995
申请日：2008-03-05
申请人： Chan-Shih Lin , Kuei-Lan Lin
发明人： Chan-Shih Lin , Kuei-Lan Lin
IPC分类号： H03M13/00
摘要： A video decoder capable of generating a check data in response to a data selection code for debugging is disclosed. The video decoder includes a plurality of functional blocks, wherein each said plurality of functional blocks has a output signal to be used as an input signal for a next stage functional block; a multiplexer (209) that receives a plurality of data extracted from said plurality of output signals from said plurality of functional blocks, and outputs one of said plurality of data according to said data selection code; and a check logic (210) that generates said check data by calculating one of said plurality of data outputted from said multiplexer.
摘要翻译： 公开了能够响应用于调试的数据选择代码生成检查数据的视频解码器。 视频解码器包括多个功能块，其中每个所述多个功能块具有用作下一级功能块的输入信号的输出信号; 多路复用器（209），其从所述多个功能块接收从所述多个输出信号提取的多个数据，并根据所述数据选择码输出所述多个数据中的一个; 以及通过计算从所述多路复用器输出的所述多个数据中的一个产生所述校验数据的校验逻辑（210）。
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公开(公告)号：US20070040714A1
公开(公告)日：2007-02-22
申请号：US11385850
申请日：2006-03-22
申请人： Roger Lin , Ting-Kun Yeh , Martin Hsu , Roy Wang , Kuei-Lan Lin
发明人： Roger Lin , Ting-Kun Yeh , Martin Hsu , Roy Wang , Kuei-Lan Lin
IPC分类号： H03M7/40
CPC分类号： H03M7/425
摘要： An device and method for variable length decoding. The device comprises a device for variable length decoding comprising a first register, a second register, a first barrel shifter, a buffer, a coding table and an adding device. The method is characterized in that the buffer is installed on the output path from the barrel shifter to the coding table so as to shorten the critical path.
摘要翻译： 一种用于可变长度解码的设备和方法。 该装置包括用于可变长度解码的装置，包括第一寄存器，第二寄存器，第一桶形移位器，缓冲器，编码表和添加装置。 该方法的特征在于缓冲器安装在从桶形移位器到编码表的输出路径上，以便缩短关键路径。
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公开(公告)号：US07327291B2
公开(公告)日：2008-02-05
申请号：US11385850
申请日：2006-03-22
申请人： Roger Lin , Ting-Kun Yeh , Martin Hsu , Roy Wang , Kuei-Lan Lin
发明人： Roger Lin , Ting-Kun Yeh , Martin Hsu , Roy Wang , Kuei-Lan Lin
IPC分类号： H03M7/40
CPC分类号： H03M7/425
摘要： An device and method for variable length decoding. The device comprises a device for variable length decoding comprising a first register, a second register, a first barrel shifter, a buffer, a coding table and an adding device. The method is characterized in that the buffer is installed on the output path from the barrel shifter to the coding table so as to shorten the critical path.
摘要翻译： 一种用于可变长度解码的设备和方法。 该装置包括用于可变长度解码的装置，包括第一寄存器，第二寄存器，第一桶形移位器，缓冲器，编码表和添加装置。 该方法的特征在于缓冲器安装在从桶形移位器到编码表的输出路径上，以便缩短关键路径。
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