公开(公告)号：US08498340B2

公开(公告)日：2013-07-30

申请号：US11397349

申请日：2006-04-04

申请人： Chan-Shih Lin

发明人： Chan-Shih Lin

IPC分类号： H04N7/12 ,  H04N11/02

CPC分类号： H04N19/426 ,  G09G5/39 ,  H04N19/44

摘要： A method of decoding and displaying video frames and an apparatus thereof are disclosed. The method includes indexing the first portion of a buffer with the first reference number, said first portion to be stored with the first reference frame; changing said first reference number to the second reference upon detecting the second reference frame to be stored in the second portion of said buffer; storing the third reference frame in the third portion of said buffer; and displaying said first reference frame associated with said second reference number, wherein storing said third reference frame in said third portion performs simultaneously with displaying said first reference frame.

摘要翻译： 公开了解码和显示视频帧的方法及其装置。 该方法包括用第一参考号索引缓冲器的第一部分，所述第一部分将与第一参考帧一起存储; 在检测要存储在所述缓冲器的第二部分中的第二参考帧时，将所述第一参考号改变为第二参考; 将所述第三参考帧存储在所述缓冲器的第三部分中; 以及显示与所述第二参考号码相关联的所述第一参考帧，其中在所述第三部分中存储所述第三参考帧同时显示所述第一参考帧。

公开(公告)号：US20090228770A1

公开(公告)日：2009-09-10

申请号：US12042995

申请日：2008-03-05

申请人： Chan-Shih Lin ,  Kuei-Lan Lin

发明人： Chan-Shih Lin ,  Kuei-Lan Lin

IPC分类号： H03M13/03

CPC分类号： H04N19/42 ,  H04N19/61

摘要： A video decoder capable of generating a check data in response to a data selection code for debugging is disclosed. The video decoder includes a plurality of functional blocks, wherein each said plurality of functional blocks has a output signal to be used as an input signal for a next stage functional block; a multiplexer (209) that receives a plurality of data extracted from said plurality of output signals from said plurality of functional blocks, and outputs one of said plurality of data according to said data selection code; and a check logic (210) that generates said check data by calculating one of said plurality of data outputted from said multiplexer.

摘要翻译： 公开了能够响应用于调试的数据选择代码生成检查数据的视频解码器。 视频解码器包括多个功能块，其中每个所述多个功能块具有用作下一级功能块的输入信号的输出信号; 多路复用器（209），其从所述多个功能块接收从所述多个输出信号提取的多个数据，并根据所述数据选择码输出所述多个数据中的一个; 以及通过计算从所述多路复用器输出的所述多个数据中的一个产生所述校验数据的校验逻辑（210）。

公开(公告)号：US07206365B2

公开(公告)日：2007-04-17

申请号：US10350590

申请日：2003-01-24

申请人： Chan-Shih Lin

发明人： Chan-Shih Lin

IPC分类号： H03D1/06 ,  H04L1/00

CPC分类号： H04L25/03057 ,  H04B1/7115

摘要： A decision sequence generating method and an associated receiver with a decision feedback equalizer (DFE) are provided. The receiver can mitigate multi-path distortion generated when data is transmitted through a multi-path channel, wherein the data is encoded into codewords, each of which comprises N chips. The receiver comprises a decision generator for generating N−1 chip decisions corresponding to first N−1 chips of a received codeword and for producing a codeword decision corresponding to the whole received codeword; and a feedback filter for reconstructing post-cursor section of the multi-path channel impulse response. The decision sequence generating method comprises sending the N−1 chip decisions into the feedback filter in order, producing the codeword decision after collecting all N chips of the received codeword, and then providing the codeword decision to the feedback filter to replace the N−1 chip decisions sent previously, thereby reconstructing the post-cursor section of the channel impulse response with more confidence.

摘要翻译： 提供了具有判决反馈均衡器（DFE）的判决序列生成方法和相关联的接收器。 接收机可以减轻当通过多路径信道发送数据时产生的多径失真，其中数据被编码成码字，每个码字包括N个码片。 该接收机包括一个决策发生器，用于产生对应于接收到的码字的第一N-1个码片的N-1码片决策，并用于产生对应于整个接收码字的码字判决; 以及用于重建多路径信道脉冲响应的后视标部分的反馈滤波器。 判决序列生成方法包括：依次将N-1个码片决定发送到反馈滤波器中，在收集所接收到的码字的所有N个码片之后产生码字判定，然后将该码字判定提供给反馈滤波器以代替N-1 先前发送的芯片决策，从而以更自信的方式重建信道脉冲响应的后光标部分。

公开(公告)号：US08254453B2

公开(公告)日：2012-08-28

申请号：US12690921

申请日：2010-01-20

申请人： Chan-Shih Lin ,  Shu-Hsien Chou ,  Kuei-Lan Lin

发明人： Chan-Shih Lin ,  Shu-Hsien Chou ,  Kuei-Lan Lin

IPC分类号： H04N7/12 ,  H04N7/26

CPC分类号： H04N19/42 ,  H04N19/12 ,  H04N19/44 ,  H04N19/46 ,  H04N19/593

摘要： A multi-format video decoder includes a bitstream buffer, a system controller, a bitstream decoding unit, an intra mode decoding unit and a shared prediction module. The system controller selectively generates a first control signal or a second control signal according to a video bitstream. The bitstream decoding unit generates a decoding information signal according to the video bitstream when receiving the first control signal. The intra mode decoding unit generates an intra mode signal when receiving the second control signal. The shared prediction module performs an AC/DC prediction upon a current block of the video bitstream to generate a current first prediction result according to the decoding information signal and performs an intra prediction upon the current block to generate a current second prediction result according to the intra mode signal. The shared prediction module includes shared components being utilized in the AC/DC prediction and the intra prediction.

摘要翻译： 多格式视频解码器包括比特流缓冲器，系统控制器，比特流解码单元，帧内模式解码单元和共享预测模块。 系统控制器根据视频比特流选择性地产生第一控制信号或第二控制信号。 比特流解码单元在接收到第一控制信号时根据视频比特流生成解码信息信号。 帧内模式解码单元在接收到第二控制信号时产生帧内模式信号。 共享预测模块对视频比特流的当前块执行AC / DC预测，根据解码信息信号产生当前第一预测结果，并根据当前块执行帧内预测，​​根据该预测结果生成当前第二预测结果 帧内模式信号。 共享预测模块包括在AC / DC预测和帧内预测中使用的共享组件。

公开(公告)号：US08094712B2

公开(公告)日：2012-01-10

申请号：US12058765

申请日：2008-03-31

申请人： Chan-Shih Lin ,  Shao-Yung Su

发明人： Chan-Shih Lin ,  Shao-Yung Su

IPC分类号： H04N11/02

CPC分类号： H04N21/435 ,  H04N21/234327 ,  H04N21/235 ,  H04N21/4331 ,  H04N21/4345 ,  H04N21/84 ,  H04N21/8456

摘要： An apparatus for processing a data stream having a hierarchical layer structure and including encoded data sets and raw data sets is provided. The apparatus includes a first processing circuit for generating an enable signal corresponding to a predetermined layer of the hierarchical layer structure when detecting that a data set of the data stream corresponds to the predetermined layer, and a second processing circuit coupled to the first processing circuit for detecting whether an identifier of the data set corresponds to one predetermined raw data set identifier when receiving the enable signal from the first processing circuit.

摘要翻译： 提供了一种用于处理具有分层结构并包括编码数据集和原始数据集的数据流的装置。 该装置包括第一处理电路，用于当检测到数据流的数据集对应于预定层时，产生对应于分级层结构的预定层的使能信号;以及第二处理电路，耦合到第一处理电路 当从第一处理电路接收到使能信号时，检测数据集的标识符是否对应于一个预定的原始数据集标识符。

公开(公告)号：US20110182348A1

公开(公告)日：2011-07-28

申请号：US12693445

申请日：2010-01-26

申请人： Chien-Chang Lin ,  Chan-Shih Lin

发明人： Chien-Chang Lin ,  Chan-Shih Lin

IPC分类号： H04N11/04 ,  G06F12/08

CPC分类号： H04N19/433 ,  H04N19/44 ,  H04N19/61

摘要： Frame data stored in an external memory is partitioned into a plurality of macroblocks, and a plurality of access units each comprising at least one macroblock are provided. A plurality of frames are fetched from the external memory by loading the plurality of access units in a predetermined sequence. A current data for decoding a macroblock of the first access unit and a reference data for decoding a macroblock of the second access unit are loaded from the first access unit, and respectively mapped to a first memory group and a second memory group of a circular cache according to the frame width.

摘要翻译： 存储在外部存储器中的帧数据被划分为多个宏块，并且提供了包括至少一个宏块的多个存取单元。 通过以预定顺序加载多个访问单元，从外部存储器取出多个帧。 用于解码第一存取单元的宏块的当前数据和用于解码第二存取单元的宏块的参考数据从第一存取单元加载，分别映射到循环缓存的第一存储组和第二存储组 根据帧宽度。

公开(公告)号：US20100226442A1

公开(公告)日：2010-09-09

申请号：US12399525

申请日：2009-03-06

申请人： Chan-Shih Lin ,  Yin-Her Su

发明人： Chan-Shih Lin ,  Yin-Her Su

IPC分类号： H04N7/26

CPC分类号： H04N19/423 ,  H04N19/44 ,  H04N19/61

摘要： A bit-stream buffer controller for a video decoder includes a first FIFO, a second FIFO, and an interrupt controller. The first FIFO is configured to store an input bit-stream. The second FIFO is configured to store a payload extracted from the input bit-stream. The interrupt controller is configured to generate an interrupt signal according to a fullness status of the first FIFO and the second FIFO such that the video decoder may be switched to load the payload without checking the fullness status each time the payload is loaded.

摘要翻译： 用于视频解码器的比特流缓冲器控制器包括第一FIFO，第二FIFO和中断控制器。 第一个FIFO被配置为存储输入比特流。 第二FIFO被配置为存储从输入比特流提取的有效载荷。 所述中断控制器被配置为根据所述第一FIFO和所述第二FIFO的丰满状态产生中断信号，使得所述视频解码器可以在每次所述有效负载被加载时检查所述有效负载而不检查所述充满状态。

公开(公告)号：US07246298B2

公开(公告)日：2007-07-17

申请号：US10990929

申请日：2004-11-17

申请人： Tzi-Dar Chiueh ,  Sung-Chiao Li ,  Chan-Shih Lin

发明人： Tzi-Dar Chiueh ,  Sung-Chiao Li ,  Chan-Shih Lin

IPC分类号： H03M13/00 ,  H03M13/03

CPC分类号： H03M13/3927 ,  H03M13/2957 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6502

摘要： A Viterbi/Turbo unified decoder supports both voice and data streams due to the ability of performing Viterbi (convolutional) decoding and Turbo decoding. The Viterbi/Turbo unified decoder of an embodiment reduces the hardware cost by computing path metrics for both Viterbi and Turbo decoding using a single control circuit. The control circuit comprises a plurality of processors and memory banks, and the routing rule for the processors to read/write the path metric information from/to the memory banks are fixed for both Viterbi and Turbo coded inputs.

摘要翻译： 由于执行维特比（卷积）解码和Turbo解码的能力，维特比/ Turbo统一解码器支持语音和数据流。 实施例的维特比/ Turbo统一解码器通过使用单个控制电路计算维特比和Turbo解码的路径度量来降低硬件成本。 控制电路包括多个处理器和存储器组，并且用于处理器从/向存储体读取/写入路径度量信息的路由规则对于维特比和Turbo编码输入是固定的。

公开(公告)号：US20050149838A1

公开(公告)日：2005-07-07

申请号：US10990929

申请日：2004-11-17

申请人： Tzi-Dar Chiueh ,  Sung-Chiao Li ,  Chan-Shih Lin

发明人： Tzi-Dar Chiueh ,  Sung-Chiao Li ,  Chan-Shih Lin

IPC分类号： H03M13/03 ,  H03M13/29 ,  H03M13/41

CPC分类号： H03M13/3927 ,  H03M13/2957 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6502

摘要： A Viterbi/Turbo unified decoder supports both voice and data streams due to the ability of performing Viterbi (convolutional) decoding and Turbo decoding. The Viterbi/Turbo unified decoder of an embodiment reduces the hardware cost by computing path metrics for both Viterbi and Turbo decoding using a single control circuit. The control circuit comprises a plurality of processors and memory banks, and the routing rule for the processors to read/write the path metric information from/to the memory banks are fixed for both Viterbi and Turbo coded inputs.

摘要翻译： 由于执行维特比（卷积）解码和Turbo解码的能力，维特比/ Turbo统一解码器支持语音和数据流。 实施例的维特比/ Turbo统一解码器通过使用单个控制电路计算维特比和Turbo解码的路径度量来降低硬件成本。 控制电路包括多个处理器和存储器组，并且用于处理器从/向存储体读取/写入路径度量信息的路由规则对于维特比和Turbo编码输入是固定的。

公开(公告)号：US20110176609A1

公开(公告)日：2011-07-21

申请号：US12690921

申请日：2010-01-20

申请人： Chan-Shih Lin ,  Shu-Hsien Chou ,  Kuei-Lan Lin

发明人： Chan-Shih Lin ,  Shu-Hsien Chou ,  Kuei-Lan Lin

IPC分类号： H04N7/32 ,  H04N7/24 ,  H04N7/26

CPC分类号： H04N19/42 ,  H04N19/12 ,  H04N19/44 ,  H04N19/46 ,  H04N19/593

摘要： A multi-format video decoder includes a bitstream buffer, a system controller, a bitstream decoding unit, an intra mode decoding unit and a shared prediction module. The system controller selectively generates a first control signal or a second control signal according to a video bitstream. The bitstream decoding unit generates a decoding information signal according to the video bitstream when receiving the first control signal. The intra mode decoding unit generates an intra mode signal when receiving the second control signal. The shared prediction module performs an AC/DC prediction upon a current block of the video bitstream to generate a current first prediction result according to the decoding information signal and performs an intra prediction upon the current block to generate a current second prediction result according to the intra mode signal. The shared prediction module includes shared components being utilized in the AC/DC prediction and the intra prediction.

摘要翻译： 多格式视频解码器包括比特流缓冲器，系统控制器，比特流解码单元，帧内模式解码单元和共享预测模块。 系统控制器根据视频比特流选择性地产生第一控制信号或第二控制信号。 比特流解码单元在接收到第一控制信号时根据视频比特流生成解码信息信号。 帧内模式解码单元在接收到第二控制信号时产生帧内模式信号。 共享预测模块对视频比特流的当前块执行AC / DC预测，根据解码信息信号产生当前第一预测结果，并根据当前块执行帧内预测，​​根据该预测结果生成当前第二预测结果 帧内模式信号。 共享预测模块包括在AC / DC预测和帧内预测中使用的共享组件。