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1.发明申请公开(公告)号：US20110119560A1
公开(公告)日：2011-05-19
申请号：US13012955
申请日：2011-01-25
申请人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
发明人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
CPC分类号： G06F11/1072 , G06F11/1068 , G06F12/0238 , G06F13/1668 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/35 , H03M13/3715
摘要： An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.
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2.发明授权Flash memory device error correction code controllers and related methods and memory systems 有权闪存设备纠错码控制器及相关方法和存储系统公开(公告)号：US07904790B2
公开(公告)日：2011-03-08
申请号：US11692992
申请日：2007-03-29
申请人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
发明人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
IPC分类号： G11C29/00
CPC分类号： G06F11/1072 , G06F11/1068 , G06F12/0238 , G06F13/1668 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/35 , H03M13/3715
摘要： An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.
摘要翻译： 用于存储M位数据（M：等于或大于2的正整数）的闪速存储器件的ECC控制器包括编码器和解码器。 编码器使用第一纠错方案生成要存储在闪速存储装置中的输入数据的第一ECC数据，并使用第二纠错方案为输入数据生成第二ECC数据。 输入数据，第一ECC数据和第二ECC数据被存储在闪存设备中。 解码器计算从闪速存储器件读取的数据中的错误数目，并且可以使用第一ECC数据和第二ECC数据中的一个选择性地基于错误数来校正读取数据中的错误。
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3.发明申请公开(公告)号：US20110119561A1
公开(公告)日：2011-05-19
申请号：US13012984
申请日：2011-01-25
申请人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
发明人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
IPC分类号： G06F11/16
CPC分类号： G06F11/1072 , G06F11/1068 , G06F12/0238 , G06F13/1668 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/35 , H03M13/3715
摘要： An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.
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4.发明申请Flash memory Device Error Correction Code Controllers and Related Methods and Memory Systems 有权闪存设备错误纠正代码控制器及相关方法和内存系统公开(公告)号：US20080168319A1
公开(公告)日：2008-07-10
申请号：US11692992
申请日：2007-03-29
申请人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
发明人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
CPC分类号： G06F11/1072 , G06F11/1068 , G06F12/0238 , G06F13/1668 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/35 , H03M13/3715
摘要： An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.
摘要翻译： 用于存储M位数据（M：等于或大于2的正整数）的闪速存储器件的ECC控制器包括编码器和解码器。 编码器使用第一纠错方案生成要存储在闪速存储装置中的输入数据的第一ECC数据，并使用第二纠错方案为输入数据生成第二ECC数据。 输入数据，第一ECC数据和第二ECC数据被存储在闪存设备中。 解码器计算从闪速存储器件读取的数据中的错误数目，并且可以使用第一ECC数据和第二ECC数据中的一个选择性地基于错误数来校正读取数据中的错误。
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5.发明授权Flash memory device error correction code controllers and related methods and memory systems 有权闪存设备纠错码控制器及相关方法和存储系统公开(公告)号：US08788905B2
公开(公告)日：2014-07-22
申请号：US13012955
申请日：2011-01-25
申请人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
发明人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
CPC分类号： G06F11/1072 , G06F11/1068 , G06F12/0238 , G06F13/1668 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/35 , H03M13/3715
摘要： An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.
摘要翻译： 用于存储M位数据（M：等于或大于2的正整数）的闪速存储器件的ECC控制器包括编码器和解码器。 编码器使用第一纠错方案生成要存储在闪速存储装置中的输入数据的第一ECC数据，并使用第二纠错方案为输入数据生成第二ECC数据。 输入数据，第一ECC数据和第二ECC数据被存储在闪速存储器件中。 解码器计算从闪速存储器件读取的数据中的错误数目，并且可以使用第一ECC数据和第二ECC数据中的一个选择性地基于错误数来校正读取数据中的错误。
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6.发明授权Flash memory device error correction code controllers and related methods and memory systems 有权闪存设备纠错码控制器及相关方法和存储系统公开(公告)号：US08112692B2
公开(公告)日：2012-02-07
申请号：US13012984
申请日：2011-01-25
申请人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
发明人： Chang-Duck Lee , Seok-won Heo , Si-Yung Park , Dong-Ryoul Lee
IPC分类号： G11C29/00
CPC分类号： G06F11/1072 , G06F11/1068 , G06F12/0238 , G06F13/1668 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/35 , H03M13/3715
摘要： An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.
摘要翻译： 用于存储M位数据（M：等于或大于2的正整数）的闪速存储器件的ECC控制器包括编码器和解码器。 编码器使用第一纠错方案生成要存储在闪速存储装置中的输入数据的第一ECC数据，并使用第二纠错方案为输入数据生成第二ECC数据。 输入数据，第一ECC数据和第二ECC数据被存储在闪存设备中。 解码器计算从闪速存储器件读取的数据中的错误数目，并且可以使用第一ECC数据和第二ECC数据中的一个选择性地基于错误数来校正读取数据中的错误。
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