公开(公告)号：US20050024348A1

公开(公告)日：2005-02-03

申请号：US10695813

申请日：2003-10-30

申请人： Chang-Ho Liou ,  Jun-Ren Shih ,  Jan-Ruei Lin

发明人： Chang-Ho Liou ,  Jun-Ren Shih ,  Jan-Ruei Lin

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2320/0276

摘要： A driving circuit for solving color dispersion is disclosed, which includes a coding unit, a reference voltage generator and at least one data driver. The coding unit generates a plurality of coded data based on three Gamma curves. The reference voltage generator receives the coded data and converts the coded data into a plurality of reference voltages, such that the data driver drives display cells on the display array in accordance with the reference voltages.

摘要翻译： 公开了一种用于解决色散的驱动电路，其包括编码单元，参考电压发生器和至少一个数据驱动器。 编码单元基于三个伽马曲线生成多个编码数据。 参考电压发生器接收编码数据并将编码数据转换成多个参考电压，使得数据驱动器根据参考电压驱动显示器阵列上的显示单元。

公开(公告)号：US20050057553A1

公开(公告)日：2005-03-17

申请号：US10760410

申请日：2004-01-21

申请人： Jun-Ren Shih ,  Chia-Pao Chang ,  Bowen Wang ,  Jan-Ruei Lin

发明人： Jun-Ren Shih ,  Chia-Pao Chang ,  Bowen Wang ,  Jan-Ruei Lin

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  H03K19/0185

CPC分类号： G09G3/3677 ,  G09G3/2096 ,  G09G2310/0267 ,  G09G2310/0289 ,  G09G2330/021

摘要： Scan driver and driving system with low input voltage and their level shift circuit are disclosed. The scan driver includes a latch unit, a level shift circuit and a buffer. The latch unit generates a first control signal and a second control signal. The level shift circuit is connected to the latch unit to receive the first control signal, the second control signal, a first clock signal and a second clock signal, so as to output a scan signal with high voltage level. The buffer enhances driving ability of the scan signal for driving thin-film transistors (TFTs) of a display panel.

摘要翻译： 公开了具有低输入电压的扫描驱动器和驱动系统及其电平移位电路。 扫描驱动器包括锁存单元，电平移位电路和缓冲器。 锁存单元产生第一控制信号和第二控制信号。 电平移位电路连接到锁存单元以接收第一控制信号，第二控制信号，第一时钟信号和第二时钟信号，以输出具有高电压电平的扫描信号。 该缓冲器增强用于驱动显示面板的薄膜晶体管（TFT）的扫描信号的驱动能力。

公开(公告)号：US07283116B2

公开(公告)日：2007-10-16

申请号：US10760410

申请日：2004-01-21

申请人： Jun-Ren Shih ,  Chia-Pao Chang ,  Bowen Wang ,  Jan-Ruei Lin

发明人： Jun-Ren Shih ,  Chia-Pao Chang ,  Bowen Wang ,  Jan-Ruei Lin

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/2096 ,  G09G2310/0267 ,  G09G2310/0289 ,  G09G2330/021

摘要： Scan driver and driving system with low input voltage and their level shift circuit are disclosed. The scan driver includes a latch unit, a level shift circuit and a buffer. The latch unit generates a first control signal and a second control signal. The level shift circuit is connected to the latch unit to receive the first control signal, the second control signal, a first clock signal and a second clock signal, so as to output a scan signal with high voltage level. The buffer enhances driving ability of the scan signal for driving thin-film transistors (TFTs) of a display panel.

摘要翻译： 公开了具有低输入电压的扫描驱动器和驱动系统及其电平移位电路。 扫描驱动器包括锁存单元，电平移位电路和缓冲器。 锁存单元产生第一控制信号和第二控制信号。 电平移位电路连接到锁存单元以接收第一控制信号，第二控制信号，第一时钟信号和第二时钟信号，以输出具有高电压电平的扫描信号。 该缓冲器增强用于驱动显示面板的薄膜晶体管（TFT）的扫描信号的驱动能力。

公开(公告)号：US06829322B2

公开(公告)日：2004-12-07

申请号：US10617782

申请日：2003-07-14

申请人： Jun-Ren Shih ,  Shang-Li Chen ,  Bo-Wen Wang ,  Jan-Ruei Lin

发明人： Jun-Ren Shih ,  Shang-Li Chen ,  Bo-Wen Wang ,  Jan-Ruei Lin

IPC分类号： G11C1900

CPC分类号： G11C19/00 ,  G11C19/28

摘要： A shift-register unit. The first transistor includes a first source/drain coupled to a first terminal, a second source/drain, and a first gate coupled to a reset signal to stop the shift-register unit outputting a pulse signal. The second transistor includes a third source/drain coupled to the second source/drain, a fourth source/drain coupled to a second terminal, and a second gate coupled to a setting signal to initial the shift-register unit. The third transistor includes a fifth source/drain coupled to an output terminal, a third gate coupled to the second source/drain and a sixth source/drain coupled to a clock signal to start outputting the pulse signal. The fourth transistor includes a seventh source/drain coupled to the first terminal, an eighth source/drain coupled to the output terminal and a fourth gate coupled to a refresh signal to set a voltage level of the shift-register unit in a standby mode.

摘要翻译： 移位寄存器单元。 第一晶体管包括耦合到第一端子的第一源极/漏极，第二源极/漏极以及耦合到复位信号的第一栅极，以停止移位寄存器单元输出脉冲信号。 第二晶体管包括耦合到第二源极/漏极的第三源极/漏极，耦合到第二端子的第四源极/漏极和耦合到设置信号的第二栅极以初始化移位寄存器单元。 第三晶体管包括耦合到输出端的第五源极/漏极，耦合到第二源极/漏极的第三栅极和耦合到时钟信号的第六源极/漏极，以开始输出脉冲信号。 第四晶体管包括耦合到第一端子的第七源极/漏极，耦合到输出端子的第八源极/漏极和耦合到刷新信号的第四栅极，以将待机模式中的移位寄存器单元的电压电平设置。

公开(公告)号：US08259774B2

公开(公告)日：2012-09-04

申请号：US12478166

申请日：2009-06-04

申请人： Chien-Yu Chan ,  Shao-Ping Hung ,  Jun-Ren Shih

发明人： Chien-Yu Chan ,  Shao-Ping Hung ,  Jun-Ren Shih

IPC分类号： H04B1/00 ,  H04L7/00

CPC分类号： H04B15/04

摘要： A spread spectrum clock signal generator for spreading an input clock signal into an output clock signal includes a clock signal delay chain for delaying the input clock signal into a delay clock signal group having a plurality of delay clock signals, a modulation controller for outputting a counter clock signal control signal, a clock signal selection circuit for selecting, from the delay clock signal group, a modulation clock signal group having a plurality of modulation clock signals, a programmable counter for generating a counting value according to a counter clock signal, and a clock signal output unit for combining the modulation clock signals into the output clock signal according to the counting value, and further generating the counter clock signal, outputted to the programmable counter, according to the counter clock signal control signal.

摘要翻译： 用于将输入时钟信号扩展为输出时钟信号的扩频时钟信号发生器包括用于将输入时钟信号延迟为具有多个延迟时钟信号的延迟时钟信号组的时钟信号延迟链，用于输出计数器的调制控制器 时钟信号控制信号，用于从延迟时钟信号组中选择具有多个调制时钟信号的调制时钟信号组的时钟信号选择电路，用于根据计数器时钟信号产生计数值的可编程计数器，以及 时钟信号输出单元，用于根据计数值将调制时钟信号组合成输出时钟信号，并根据计数器时钟信号控制信号进一步产生输出到可编程计数器的计数器时钟信号。

公开(公告)号：US06552708B1

公开(公告)日：2003-04-22

申请号：US09657259

申请日：2000-09-07

申请人： Bo-Wen Wang ,  Jun-Ren Shih ,  Shang-Li Chen

发明人： Bo-Wen Wang ,  Jun-Ren Shih ,  Shang-Li Chen

IPC分类号： G04G336

CPC分类号： G09G3/2011 ,  G09G3/3648 ,  G09G3/3685 ,  G09G2310/0291 ,  H03F3/505

摘要： The present invention is related to a unit gain buffer of the driver circuit to drive the data line in the filed of LCD data driver, further to be preferably applied to the new TFT-LCD processing of low temperature poly-silicon. This invention is using the plurality of PMOS transistor connection to result in the almost same value between the Vout and Vin. There is no using of the feedback connection in this invention, so the using of the compensation capacitor can be avoided, furthermore the data driver layout area of the LCD driver can be reduced. This invention can improve the defect of the larger layout area result from the prior art.

摘要翻译： 本发明涉及用于驱动LCD数据驱动器领域的数据线的驱动电路的单位增益缓冲器，进一步优选地应用于低温多晶硅的新TFT-LCD处理。 本发明使用多个PMOS晶体管连接导致Vout和Vin之间几乎相同的值。 在本发明中没有使用反馈连接，因此可以避免使用补偿电容器，此外可以降低LCD驱动器的数据驱动器布局面积。 本发明可以改善现有技术中较大布局区域结果的缺陷。

公开(公告)号：US20090323768A1

公开(公告)日：2009-12-31

申请号：US12478166

申请日：2009-06-04

申请人： Chien-Yu Chan ,  Shao-Ping Hung ,  Jun-Ren Shih

发明人： Chien-Yu Chan ,  Shao-Ping Hung ,  Jun-Ren Shih

IPC分类号： H04B1/00

CPC分类号： H04B15/04

摘要： A spread spectrum clock signal generator for spreading an input clock signal into an output clock signal includes a clock signal delay chain for delaying the input clock signal into a delay clock signal group having a plurality of delay clock signals, a modulation controller for outputting a counter clock signal control signal, a clock signal selection circuit for selecting, from the delay clock signal group, a modulation clock signal group having a plurality of modulation clock signals, a programmable counter for generating a counting value according to a counter clock signal, and a clock signal output unit for combining the modulation clock signals into the output clock signal according to the counting value, and further generating the counter clock signal, outputted to the programmable counter, according to the counter clock signal control signal.

摘要翻译： 用于将输入时钟信号扩展为输出时钟信号的扩频时钟信号发生器包括用于将输入时钟信号延迟为具有多个延迟时钟信号的延迟时钟信号组的时钟信号延迟链，用于输出计数器的调制控制器 时钟信号控制信号，用于从延迟时钟信号组中选择具有多个调制时钟信号的调制时钟信号组的时钟信号选择电路，用于根据计数器时钟信号产生计数值的可编程计数器，以及 时钟信号输出单元，用于根据计数值将调制时钟信号组合成输出时钟信号，并根据计数器时钟信号控制信号进一步产生输出到可编程计数器的计数器时钟信号。

公开(公告)号：US06937219B2

公开(公告)日：2005-08-30

申请号：US10107358

申请日：2002-03-28

申请人： Chain-Ru Chen ,  Shang-Li Chen ,  Jun-Ren Shih

发明人： Chain-Ru Chen ,  Shang-Li Chen ,  Jun-Ren Shih

IPC分类号： G09G3/32 ,  G09G3/36

CPC分类号： G09G3/3241 ,  G09G2300/0842 ,  G09G2320/0219

摘要： The main differences between the present invention the conventional pixel circuit for active matrix of current driving device is the usage of the auxiliary transistor(s). In the invention, at least one auxiliary transistor is used to separate both the transistor, which is directly electrically coupled to the current driving device, and the plate, which is not directly electrically coupled with a constant voltage source, of the capacitor from the other transistors of the pixel circuit. Hence, all circuit and voltage, which are induced by the switching process of these transistors, are blocked or compensate by the auxiliary transistor(s), and the stored voltage of the capacitor would be unaffected.

摘要翻译： 本发明的传统的电流驱动装置的有源矩阵像素电路的主要区别在于辅助晶体管的使用。 在本发明中，使用至少一个辅助晶体管将直接电耦合到电流驱动装置的晶体管与电容器与其它电极不直接电耦合的恒定电压源的二极管 像素电路的晶体管。 因此，由这些晶体管的开关过程引起的所有电路和电压被辅助晶体管阻挡或补偿，并且电容器的存储电压将不受影响。

公开(公告)号：US06891520B2

公开(公告)日：2005-05-10

申请号：US10232705

申请日：2002-09-03

申请人： Shang-Li Chen ,  Chien-Ru Chen ,  Jun-Ren Shih

发明人： Shang-Li Chen ,  Chien-Ru Chen ,  Jun-Ren Shih

IPC分类号： H01L51/50 ,  G09G3/20 ,  G09G3/30 ,  G09G3/32

CPC分类号： G09G3/3241 ,  G09G3/325 ,  G09G2300/0842 ,  G09G2320/0233

摘要： A circuit for driving active matrix LED pixels, having a capacitor, a light emitting diode, and a first and second transistor. The capacitor is connected between a gate and source of the first transistor, and the second transistor has a source connected to a drain of the first transistor and a gate connected to receive a first voltage by which the first and second transistor operates in a saturation region, and a current switch controlled by a scan signal, wherein a first current corresponding to a data signal flows through the first and second transistor to generate a second voltage stored on the capacitor when the current switch is closed, and a second current through the first and second transistor is generated by the second voltage stored on the capacitor to turn on the light emitting diode when the current switch is opened.

摘要翻译： 用于驱动有源矩阵LED像素的电路，具有电容器，发光二极管以及第一和第二晶体管。 电容器连接在第一晶体管的栅极和源极之间，并且第二晶体管具有连接到第一晶体管的漏极的源极和连接的栅极，以接收第一和第二晶体管在饱和区域中工作的第一电压 以及由扫描信号控制的电流开关，其中对应于数据信号的第一电流流过所述第一和第二晶体管，以在所述电流开关闭合时产生存储在所述电容器上的第二电压，以及通过所述第一电流的第二电流 并且当电流开关断开时，通过存储在电容器上的第二电压产生第二晶体管，以接通发光二极管。

公开(公告)号：US20110032247A1

公开(公告)日：2011-02-10

申请号：US12821373

申请日：2010-06-23

申请人： Chiu-Hsia Hsieh ,  Jun-Ren Shih ,  Shang-Ping Tang

发明人： Chiu-Hsia Hsieh ,  Jun-Ren Shih ,  Shang-Ping Tang

IPC分类号： G09G5/00

CPC分类号： G09G3/20 ,  G09G2310/027 ,  G09G2330/06 ,  G09G2340/0492 ,  G09G2370/08

摘要： A driving circuit for a display system is provided. The driving circuit includes two driving units. After receiving N image data, the first driving unit drives the display system based on M image data among the N image data. The second driving unit receives the other (N−M) image data and a set of control signals from the first driving unit. The second driving unit drives the display system based on the (N−M) image data and the set of control signals. The first driving unit adjusts the timing sequence of the set of control signals according to the mode of the display system.

摘要翻译： 提供了一种用于显示系统的驱动电路。 驱动电路包括两个驱动单元。 在接收到N个图像数据之后，第一驱动单元基于N个图像数据中的M个图像数据驱动显示系统。 第二驱动单元从第一驱动单元接收另一（N-M）个图像数据和一组控制信号。 第二驱动单元基于（N-M）图像数据和一组控制信号来驱动显示系统。 第一驱动单元根据显示系统的模式调整该组控制信号的定时顺序。