公开(公告)号：US07936021B2

公开(公告)日：2011-05-03

申请号：US11976252

申请日：2007-10-23

申请人： Chang-Hoon Jeon ,  Satoru Yamada ,  Sang-Yeon Han ,  Jong-Man Park ,  Si-Ok Sohn

发明人： Chang-Hoon Jeon ,  Satoru Yamada ,  Sang-Yeon Han ,  Jong-Man Park ,  Si-Ok Sohn

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/108

CPC分类号： H01L29/7851 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： In a fin field effect transistor (Fin FET) and a method of manufacturing the Fin FET, the Fin FET includes an active pattern inside which insulating layer patterns are formed, an isolation layer pattern enclosing a sidewall of the active pattern such that an opening exposing a sidewall of the active pattern located between the insulating layer patterns is formed, a gate electrode formed on the active pattern to fill the opening, impurity regions formed at portions of the active pattern adjacent to sidewalls of the gate electrode, an insulating interlayer covering the active pattern and the gate electrode and contact plugs formed through portions of the insulating interlayer and the active pattern adjacent to the sidewalls of the gate electrode such that the contact plug makes contact with the impurity region.

摘要翻译： 在翅片场效应晶体管（Fin FET）和制造Fin FET的方法中，Fin FET包括其中形成绝缘层图案的有源图案，包围有源图案的侧壁的隔离层图案，使得开口露出 形成位于绝缘层图案之间的有源图案的侧壁，形成在有源图案上以填充开口的栅电极，形成在与栅电极的侧壁相邻的有源图案的部分处的杂质区，覆盖 有源图案和通过绝缘夹层的一部分和与栅电极的侧壁相邻的有源图案形成的栅电极和接触插塞，使得接触插塞与杂质区接触。

公开(公告)号：US20080099850A1

公开(公告)日：2008-05-01

申请号：US11976252

申请日：2007-10-23

申请人： Chang-Hoon Jeon ,  Satoru Yamada ,  Sang-Yeon Han ,  Jong-Man Park ,  Si-Ok Sohn

发明人： Chang-Hoon Jeon ,  Satoru Yamada ,  Sang-Yeon Han ,  Jong-Man Park ,  Si-Ok Sohn

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： In a fin field effect transistor (Fin FET)and a method of manufacturing the Fin FET, the Fin FET includes an active pattern inside which insulating layer patterns are formed, an isolation layer pattern enclosing a sidewall of the active pattern such that an opening exposing a sidewall of the active pattern located between the insulating layer patterns is formed, a gate electrode formed on the active pattern to fill the opening, impurity regions formed at portions of the active pattern adjacent to sidewalls of the gate electrode, an insulating interlayer covering the active pattern and the gate electrode and contact plugs formed through portions of the insulating interlayer and the active pattern adjacent to the sidewalls of the gate electrode such that the contact plug makes contact with the impurity region.

摘要翻译： 在翅片场效应晶体管（Fin FET）和制造Fin FET的方法中，Fin FET包括其中形成绝缘层图案的有源图案，包围有源图案的侧壁的隔离层图案，使得开口露出 形成位于绝缘层图案之间的有源图案的侧壁，形成在有源图案上以填充开口的栅电极，形成在与栅电极的侧壁相邻的有源图案的部分处的杂质区，覆盖 有源图案和通过绝缘夹层的一部分和与栅电极的侧壁相邻的有源图案形成的栅电极和接触插塞，使得接触插塞与杂质区接触。

公开(公告)号：US07795678B2

公开(公告)日：2010-09-14

申请号：US12137573

申请日：2008-06-12

申请人： Jong-Man Park ,  Satoru Yanada ,  Sang-Yeon Han ,  Jun-Bum Lee ,  Si-Ok Sohn

发明人： Jong-Man Park ,  Satoru Yanada ,  Sang-Yeon Han ,  Jun-Bum Lee ,  Si-Ok Sohn

IPC分类号： H01L29/739

CPC分类号： H01L21/76232 ,  H01L27/10876 ,  H01L27/10894

摘要： A semiconductor device includes a buried isolation pattern between an active pattern on which transistors are formed and a substrate. The active pattern has adjacent sections each extending longitudinally in a first direction. A field isolation pattern is interposed between the adjacent sections of the active pattern. The buried isolation pattern has sections spaced apart from each other in the first direction under each section of the active pattern. Each section of the buried isolation pattern extends from a lower portion of the field isolation pattern in a second direction perpendicular to the first direction. At least one gate structure is disposed on each section of the active pattern, and an impurity region is located adjacent to the gate structure at the upper surface of the active pattern. The impurity region is spaced from the buried isolation pattern in a third direction perpendicular to the first and second directions. The buried isolation pattern offers a control on the body effect caused by a bias applied to the substrate.

摘要翻译： 半导体器件包括在其上形成晶体管的有源图案和衬底之间的掩埋隔离图案。 有源图案具有各自沿第一方向纵向延伸的相邻部分。 场隔离图案插入在活动图案的相邻部分之间。 埋置隔离图案具有在活动图案的每个部分下沿第一方向彼此间隔开的部分。 掩埋隔离图案的每个部分在垂直于第一方向的第二方向上从场隔离图案的下部延伸。 至少一个栅极结构设置在有源图案的每个部分上，并且杂质区域位于活性图案的上表面处的栅极结构附近。 杂质区域与第一和第二方向垂直的第三方向与掩埋隔离图案间隔开。 掩埋隔离图案提供了由施加到基底的偏压引起的身体效应的控制。