公开(公告)号：US20070195569A1

公开(公告)日：2007-08-23

申请号：US11697101

申请日：2007-04-05

申请人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Soo Chang ,  Jeo-Jin Lyu

发明人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Soo Chang ,  Jeo-Jin Lyu

IPC分类号： G11C19/08

CPC分类号： G02F1/13458 ,  G02F1/13306 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1255

摘要： In a method of fabricating a liquid crystal display an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.

摘要翻译： 在制造液晶显示器的方法中，用于存储电容器的绝缘层的厚度减小以增加存储容量，同时以稳定的方式保持开口率。 用于液晶显示器的薄膜晶体管阵列面板包括绝缘基板，以及形成在绝缘基板上的栅极线组件和辅助电容器线组件。 栅极线组件具有栅极线和栅电极。 栅极绝缘层覆盖栅极线组件和存储电容器线组件。 在栅极绝缘层上形成半导体图形。 在与半导体图案重叠的栅极绝缘层上形成数据线组合和存储电容器导电图案。 数据线组件具有数据线源电极和漏电极。 存储电容器导电图案与辅助电容线组合部分重叠，从而形成第一存储电容器。 钝化层覆盖数据线组件，存储电容器导电图案和半导体图案。 在钝化层处形成第一和第二接触孔，同时使漏电极和存储电容器导电图案暴露。 像素电极形成在钝化层上，同时通过第一和第二接触孔连接到漏电极和存储电容器导电图案。 像素电极与存储电容器线路组件的一部分相关联地形成第二存储电容器。

公开(公告)号：US07868953B2

公开(公告)日：2011-01-11

申请号：US11697101

申请日：2007-04-05

申请人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Soo Chang ,  Jae-Jin Lyu

发明人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Soo Chang ,  Jae-Jin Lyu

IPC分类号： G02F1/1343

CPC分类号： G02F1/13458 ,  G02F1/13306 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1255

摘要： In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.

公开(公告)号：US07209192B2

公开(公告)日：2007-04-24

申请号：US10432833

申请日：2002-02-27

申请人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

发明人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

IPC分类号： G02F1/1343

CPC分类号： G02F1/13458 ,  G02F1/13306 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1255

摘要： In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.

摘要翻译： 在制造液晶显示器的方法中，用于存储电容器的绝缘层的厚度减小以增加存储容量，同时以稳定的方式保持开口率。 用于液晶显示器的薄膜晶体管阵列面板包括绝缘基板，以及形成在绝缘基板上的栅极线组件和辅助电容器线组件。 栅极线组件具有栅极线和栅电极。 栅极绝缘层覆盖栅极线组件和存储电容器线组件。 在栅极绝缘层上形成半导体图形。 在与半导体图案重叠的栅极绝缘层上形成数据线组合和存储电容器导电图案。 数据线组件具有数据线，源电极和漏电极。 存储电容器导电图案与辅助电容线组合部分重叠，从而形成第一存储电容器。 钝化层覆盖数据线组件，存储电容器导电图案和半导体图案。 在钝化层处形成第一和第二接触孔，同时使漏电极和存储电容器导电图案暴露。 像素电极形成在钝化层上，同时通过第一和第二接触孔连接到漏电极和存储电容器导电图案。 像素电极与存储电容器线路组件的一部分相关联地形成第二存储电容器。

公开(公告)号：US07990484B2

公开(公告)日：2011-08-02

申请号：US11697122

申请日：2007-04-05

申请人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

发明人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

IPC分类号： G02F1/1343

CPC分类号： G02F1/136213 ,  H01L27/1255

摘要： In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.

摘要翻译： 在制造液晶显示器的方法中，用于存储电容器的绝缘层的厚度减小以增加存储容量，同时以稳定的方式保持开口率。 用于液晶显示器的薄膜晶体管阵列面板包括绝缘基板，以及形成在绝缘基板上的栅极线组件和辅助电容器线组件。 栅极线组件具有栅极线和栅电极。 栅极绝缘层覆盖栅极线组件和存储电容器线组件。 在栅极绝缘层上形成半导体图形。 在与半导体图案重叠的栅极绝缘层上形成数据线组合和存储电容器导电图案。 数据线组件具有数据线，源电极和漏电极。 存储电容器导电图案与辅助电容线组合部分重叠，从而形成第一存储电容器。 钝化层覆盖数据线组件，存储电容器导电图案和半导体图案。 在钝化层处形成第一和第二接触孔，同时使漏电极和存储电容器导电图案暴露。 像素电极形成在钝化层上，同时通过第一和第二接触孔连接到漏电极和存储电容器导电图案。 像素电极与存储电容器线路组件的一部分相关联地形成第二存储电容器。

公开(公告)号：US20070176178A1

公开(公告)日：2007-08-02

申请号：US11697174

申请日：2007-04-05

申请人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

发明人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

IPC分类号： H01L29/04 ,  G02F1/136

CPC分类号： G02F1/13458 ,  G02F1/13306 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1255

摘要： In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.

摘要翻译： 在制造液晶显示器的方法中，用于存储电容器的绝缘层的厚度减小以增加存储容量，同时以稳定的方式保持开口率。 用于液晶显示器的薄膜晶体管阵列面板包括绝缘基板，以及形成在绝缘基板上的栅极线组件和辅助电容器线组件。 栅极线组件具有栅极线和栅电极。 栅极绝缘层覆盖栅极线组件和存储电容器线组件。 在栅极绝缘层上形成半导体图形。 在与半导体图案重叠的栅极绝缘层上形成数据线组合和存储电容器导电图案。 数据线组件具有数据线，源电极和漏电极。 存储电容器导电图案与辅助电容线组合部分重叠，从而形成第一存储电容器。 钝化层覆盖数据线组件，存储电容器导电图案和半导体图案。 在钝化层处形成第一和第二接触孔，同时使漏电极和存储电容器导电图案暴露。 像素电极形成在钝化层上，同时通过第一和第二接触孔连接到漏电极和存储电容器导电图案。 像素电极与存储电容器线路组件的一部分相关联地形成第二存储电容器。

公开(公告)号：US08040446B2

公开(公告)日：2011-10-18

申请号：US11697083

申请日：2007-04-05

申请人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

发明人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

IPC分类号： G02F1/1343

CPC分类号： G02F1/13458 ,  G02F1/13306 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1255

摘要： In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.

公开(公告)号：US07916227B2

公开(公告)日：2011-03-29

申请号：US11697122

申请日：2007-04-05

申请人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

发明人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

IPC分类号： G02F1/1343

摘要： In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.

公开(公告)号：US20070190703A1

公开(公告)日：2007-08-16

申请号：US11697122

申请日：2007-04-05

申请人： Chung-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

发明人： Chung-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

IPC分类号： H01L21/84

CPC分类号： G02F1/136213 ,  H01L27/1255

摘要： In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.

公开(公告)号：US20070188669A1

公开(公告)日：2007-08-16

申请号：US11697083

申请日：2007-04-05

申请人： Chang Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

发明人： Chang Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

IPC分类号： G02F1/1343

CPC分类号： G02F1/13458 ,  G02F1/13306 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1255

摘要： In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.