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    CURRENT-DRIVEN MAGNETIC DOMAIN-WALL LOGIC
    1.
    发明公开
    CURRENT-DRIVEN MAGNETIC DOMAIN-WALL LOGIC 审中-公开

    公开(公告)号：US20230352109A1

    公开(公告)日：2023-11-02

    申请号：US17909490

    申请日：2021-01-26

    申请人： Paul Scherrer Institut

    发明人： Zhaochu Luo ,  Ales Hrabec ,  Laura J. Heyderman ,  Pietro Gambardella ,  Trong Phuong Dao

    IPC分类号： G11C19/08 ,  H10N50/10 ,  G11C11/16 ,  H10N52/80 ,  H10N50/85 ,  H03K19/18

    CPC分类号： G11C19/0841 ,  H10N50/10 ,  G11C11/161 ,  H10N52/80 ,  H10N50/85 ,  H03K19/18

    摘要： A spin-based logic architecture provides nonvolatile data retention, near-zero leakage, and scalability. The architecture based on magnetic domain-walls take advantage of fast domain-wall motion, high density, non-volatility, and flexible design in order to process and store information. There is disclosed a concept to perform all-electric logic operations and cascading in domain-wall racetracks. The novel system exploits chiral coupling between neighboring magnetic domains induced by the interfacial Dzyaloshinskii-Moriya interaction to realize a domain-wall inverter. There are described reconfigurable NAND and NOR logic gates that perform operations with current-induced domain-wall motion. Several NAND gates are cascaded to build XOR and full adder gates, demonstrating electrical control of magnetic data and device interconnection in logic circuits. The novel system provides a viable platform for scalable all-electric magnetic logic and paves the way for memory-in-logic applications.

    Semiconductor device with first-in-first-out circuit
    2.
    发明授权
    Semiconductor device with first-in-first-out circuit 有权

    公开(公告)号：US11805638B2

    公开(公告)日：2023-10-31

    申请号：US17202144

    申请日：2021-03-15

    申请人： Micron Technology, Inc.

    发明人： Seiji Narui ,  Yuki Ebihara

    IPC分类号： G11C19/08 ,  H10B12/00 ,  G11C11/4074 ,  G11C19/28 ,  G06F5/06

    CPC分类号： H10B12/315 ,  G06F5/06 ,  G11C11/4074 ,  G11C19/0875 ,  G11C19/287

    摘要： Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.

    Memory system and shift register memory
    3.
    发明授权
    Memory system and shift register memory 有权

    公开(公告)号：US11675535B2

    公开(公告)日：2023-06-13

    申请号：US17015893

    申请日：2020-09-09

    申请人： Kioxia Corporation

    发明人： Yuta Aiba ,  Naomi Takeda ,  Masanobu Shirakawa

    IPC分类号： G06F3/06 ,  G11C19/08

    CPC分类号： G06F3/0659 ,  G06F3/0608 ,  G06F3/0679 ,  G11C19/0841

    摘要： According to one embodiment, a memory system includes a shift register memory and a controller. The shift register memory includes data storing shift strings. The controller changes a shift pulse, which is to be applied to the data storing shift strings from which first data is read by applying a first shift pulse, to a second shift pulse to write second data to the data storing shift strings and to read the second data from the data storing shift strings. The controller creates likelihood information of data read from the data storing shift strings in accordance with a read result of the second data. The controller performs soft decision decoding for the first data using the likelihood information.

    SEMICONDUCTOR CIRCUIT, CONTROL METHOD OF SEMICONDUCTOR CIRCUIT, AND ELECTRONIC APPARATUS
    6.
    发明申请
    SEMICONDUCTOR CIRCUIT, CONTROL METHOD OF SEMICONDUCTOR CIRCUIT, AND ELECTRONIC APPARATUS 审中-公开

    公开(公告)号：US20190228829A1

    公开(公告)日：2019-07-25

    申请号：US16336815

    申请日：2017-08-23

    申请人： SONY CORPORATION

    发明人： Keizo HIRAGA

    IPC分类号： G11C19/08 ,  G11C29/50 ,  G01R31/3177 ,  G06F11/10 ,  G11C29/52

    摘要： A semiconductor circuit of the disclosure includes; a sequential circuit unit including a plurality of logic circuit units that include respective flip flops and respective non-volatile storage elements, the sequential circuit unit performing, in a first term, store operation in which the storage elements in the plurality of the logic circuit units store respective voltage states in the plurality of the logic circuit units, and shift operation in which the flip flops in the plurality of the logic circuit units operate as a shift register; and a first memory that stores, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to the first data.