公开(公告)号：US20110211416A1

公开(公告)日：2011-09-01

申请号：US13105414

申请日：2011-05-11

申请人： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

发明人： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC分类号： G11C8/18

CPC分类号： H03H11/26

摘要： Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

公开(公告)号：US07965582B2

公开(公告)日：2011-06-21

申请号：US12157287

申请日：2008-06-09

申请人： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

发明人： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC分类号： G11C8/18

CPC分类号： H03H11/26

摘要： Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

摘要翻译： 用于恢复高度集成的半导体存储装置中的时钟数据的电路和方法包括：多个信号接收单元，被配置为通过多个输入/输出焊盘接收信号，并根据接收的参考时钟传送信号，信号接收单元被分成 多个相位检测单元，被配置为检测从信号接收单元的组输出的信号的相位;多个相位检测控制单元，被配置为控制相位检测单元，使得相位检测单元顺序地检测相位检测单元的相位; 从信号接收单元的每个组输出的信号和被配置为输出从相位检测单元输出的信号的通知单元。

公开(公告)号：US20090273493A1

公开(公告)日：2009-11-05

申请号：US12215772

申请日：2008-06-30

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.

摘要翻译： 并行转换器包括：数据输入单元，被配置为通过使用具有不同相位的多个时钟信号来接收多个并行数据;以及并行到串行转换单元，被配置为顺序地选择和输出 数据输入单元通过使用与数据输入单元中使用的多个时钟信号具有预定相位差的多个时钟信号。

公开(公告)号：US20090273385A1

公开(公告)日：2009-11-05

申请号：US12347446

申请日：2008-12-31

申请人： Chang-Kyu CHOI ,  Kyung-Hoon Kim

发明人： Chang-Kyu CHOI ,  Kyung-Hoon Kim

IPC分类号： H03L5/00

CPC分类号： H03K5/08 ,  H04L25/0264 ,  H04L25/028

摘要： An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

摘要翻译： 半导体器件的输出电路包括：信号选择器，被配置为接收第一和第二输入数据信号，并响应于相位信号顺序地输出第一和第二输入数据信号; 以及输出电平控制器，被配置为基于第一和第二输入数据信号来控制信号选择器的输出信号的电压电平。

公开(公告)号：US20090115485A1

公开(公告)日：2009-05-07

申请号：US12157287

申请日：2008-06-09

申请人： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

发明人： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC分类号： H03H11/26

CPC分类号： H03H11/26

摘要： Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

摘要翻译： 用于恢复高度集成的半导体存储装置中的时钟数据的电路和方法包括：多个信号接收单元，被配置为通过多个输入/输出焊盘接收信号，并根据接收的参考时钟传送信号，信号接收单元被分成 多个相位检测单元，被配置为检测从信号接收单元的组输出的信号的相位;多个相位检测控制单元，被配置为控制相位检测单元，使得相位检测单元顺序地检测相位检测单元的相位; 从信号接收单元的每个组输出的信号和被配置为输出从相位检测单元输出的信号的通知单元。

公开(公告)号：US20110156791A1

公开(公告)日：2011-06-30

申请号：US13043873

申请日：2011-03-09

申请人： Chang-Kyu Choi ,  Kyung-Hoon Kim

发明人： Chang-Kyu Choi ,  Kyung-Hoon Kim

IPC分类号： H03L5/00

CPC分类号： H03K5/08 ,  H04L25/0264 ,  H04L25/028

摘要： An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

摘要翻译： 半导体器件的输出电路包括：信号选择器，被配置为接收第一和第二输入数据信号，并响应于相位信号顺序地输出第一和第二输入数据信号; 以及输出电平控制器，被配置为基于第一和第二输入数据信号来控制信号选择器的输出信号的电压电平。

公开(公告)号：US07924060B2

公开(公告)日：2011-04-12

申请号：US12347446

申请日：2008-12-31

申请人： Chang-Kyu Choi ,  Kyung-Hoon Kim

发明人： Chang-Kyu Choi ,  Kyung-Hoon Kim

IPC分类号： H03K19/20

CPC分类号： H03K5/08 ,  H04L25/0264 ,  H04L25/028

摘要： An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

摘要翻译： 半导体器件的输出电路包括：信号选择器，被配置为接收第一和第二输入数据信号，并响应于相位信号顺序地输出第一和第二输入数据信号; 以及输出电平控制器，被配置为基于第一和第二输入数据信号来控制信号选择器的输出信号的电压电平。

公开(公告)号：US08248103B2

公开(公告)日：2012-08-21

申请号：US13043873

申请日：2011-03-09

申请人： Chang-Kyu Choi ,  Kyung-Hoon Kim

发明人： Chang-Kyu Choi ,  Kyung-Hoon Kim

IPC分类号： H03K19/0175

CPC分类号： H03K5/08 ,  H04L25/0264 ,  H04L25/028

摘要： An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

摘要翻译： 半导体器件的输出电路包括：信号选择器，被配置为接收第一和第二输入数据信号，并响应于相位信号顺序地输出第一和第二输入数据信号; 以及输出电平控制器，被配置为基于第一和第二输入数据信号来控制信号选择器的输出信号的电压电平。

公开(公告)号：US08194496B2

公开(公告)日：2012-06-05

申请号：US13105431

申请日：2011-05-11

申请人： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

发明人： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC分类号： G11C8/18

CPC分类号： H03H11/26

摘要： Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

公开(公告)号：US07796064B2

公开(公告)日：2010-09-14

申请号：US12215772

申请日：2008-06-30

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.

摘要翻译： 并行转换器包括：数据输入单元，被配置为通过使用具有不同相位的多个时钟信号来接收多个并行数据;以及并行到串行转换单元，被配置为顺序地选择和输出 数据输入单元通过使用与数据输入单元中使用的多个时钟信号具有预定相位差的多个时钟信号。