公开(公告)号：US11798881B2

公开(公告)日：2023-10-24

申请号：US17322000

申请日：2021-05-17

申请人： Changxin Memory Technologies, Inc.

发明人： Chih Cheng Liu

IPC分类号： H01L23/525 ,  H01L23/528 ,  H01L21/311

CPC分类号： H01L23/5252 ,  H01L21/311 ,  H01L23/5283

摘要： An anti-fuse structure, a method for fabricating the anti-fuse structure, and a semiconductor device are disclosed. The anti-fuse structure includes a semiconductor substrate, a fuse oxide layer, a gate material layer, a first electrode and a second electrode. An active area is defined on the semiconductor substrate by an isolation structure. The active area includes a wide portion and a narrow portion connected to each other. The fuse oxide layer is located on the semiconductor substrate, covers the narrow portion and extends to cover a first part of the wide portion. The gate material layer is formed on the fuse oxide layer. The first electrode is formed on and electrically connected to the gate material layer, while the second electrode is formed on and electrically connected to a second part of the wide portion not covered by the fuse oxide layer.

公开(公告)号：US10885956B2

公开(公告)日：2021-01-05

申请号：US16878481

申请日：2020-05-19

申请人： Changxin Memory Technologies, Inc.

发明人： Chih Cheng Liu

IPC分类号： G11C7/12 ,  G11C8/14 ,  H01L27/108

摘要： A semiconductor layout structure for a dynamic random access memory (DRAM) array, comprising an isolation structure and a plurality of active areas situated in a semiconductor substrate, each of the active areas extending along a length-wise central axis. The isolation structure is situated among the active areas. The active areas are arranged in an array and comprise a plurality of first active areas and a plurality of second active areas. The first active areas are arranged along a first length-wise direction of the active areas. The second active areas are arranged along a second length-wise direction of the active areas. The first active areas are parallel and adjacent to the second active areas, and the first and second active areas are alternately distributed in a direction of word-lines. The first active area having a first width smaller than a second width of the second active area.

公开(公告)号：US11043450B2

公开(公告)日：2021-06-22

申请号：US16882195

申请日：2020-05-22

申请人： Changxin Memory Technologies, Inc.

发明人： Chih Cheng Liu

IPC分类号： H01L21/8234 ,  H01L23/525 ,  H01L21/311 ,  H01L23/528

摘要： An anti-fuse structure, a method for fabricating the anti-fuse structure, and a semiconductor device are disclosed. The anti-fuse structure includes a semiconductor substrate, a fuse oxide layer, a gate material layer, a first electrode and a second electrode. An active area is defined on the semiconductor substrate by an isolation structure. The active area includes a wide portion and a narrow portion connected to each other. The fuse oxide layer is located on the semiconductor substrate, covers the narrow portion and extends to cover a first part of the wide portion. The gate material layer is formed on the fuse oxide layer. The first electrode is formed on and electrically connected to the gate material layer, while the second electrode is formed on and electrically connected to a second part of the wide portion not covered by the fuse oxide layer.

公开(公告)号：US11387239B2

公开(公告)日：2022-07-12

申请号：US16810572

申请日：2020-03-05

申请人： Changxin Memory Technologies, Inc.

发明人： Chih Cheng Liu

IPC分类号： H01L27/108

摘要： A transistor structure of a semiconductor memory device comprises: an active area having a plurality of trenches and a substrate surface, the trenches having openings oriented toward the substrate surface; a plurality of gate structures embedded in the trenches, wherein the substrate surface comprises source regions located on outer sides of the gate structures and a drain region located between the gate structures; node contacts each disposed on one of the source regions; a bit line contact disposed on the drain region and connectable to a bit line, the node contacts sharing the bit line contact through adjacent gate structures, wherein the drain region comprises a first ion implantation layer extending inwardly from the bit line contact, each of the source regions comprising a second ion implantation layer extending inwardly from a corresponding node contact, the first ion implantation layer being deeper than the second ion implantation layer.

公开(公告)号：US11342292B2

公开(公告)日：2022-05-24

申请号：US17015223

申请日：2020-09-09

申请人： Changxin Memory Technologies, Inc.

发明人： Chih Cheng Liu

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/00

摘要： A bonding pad structure and a method thereof includes: a base metal layer formed on a substrate; first conductive vias arranged in a peripheral region of the base metal layer; an intermediate buffer layer formed above the base metal layer, the intermediate buffer layer spaced from and aligned with the base metal layer, the first conductive vias vertically connecting the base metal layer and the intermediate buffer layer; second conductive vias arranged in a peripheral region of the intermediate buffer layer; a surface bonding layer formed above the intermediate buffer layer, the surface bonding layer spaced from and aligned with the intermediate buffer layer, the second conductive vias vertically connecting the intermediate buffer layer and the surface bonding layer, the intermediate buffer layer comprising a mesh structure, and the first conductive vias and the second conductive vias not vertically aligned with a central region of the intermediate buffer layer.

公开(公告)号：US11189621B2

公开(公告)日：2021-11-30

申请号：US16850469

申请日：2020-04-16

申请人： Changxin Memory Technologies, Inc.

发明人： Chih Cheng Liu

IPC分类号： H01L27/108 ,  H01L21/762 ,  H01L29/06

摘要： A semiconductor layout structure for a dynamic random access memory (DRAM) array comprises a plurality of active areas, an isolation structure and a plurality of word lines in a semiconductor substrate, where the isolation structure is situated among the plurality of active areas. Each of the plurality of active areas comprises a first segment extending in a first direction and a second segment extending in a second direction, one end of the first segment connected to an end of the second segment such that the active area presents a “V” shape. Two of the plurality of word lines intersect and traverse the first and second segments in each of the active areas respectively.