公开(公告)号：US08436801B2

公开(公告)日：2013-05-07

申请号：US12684908

申请日：2010-01-09

申请人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

发明人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

IPC分类号： G09G3/36

CPC分类号： H03K19/0175 ,  G09G3/3677 ,  G09G2310/0289 ,  G09G2330/023

摘要： A level shift circuit includes a control logic circuit, a plurality of level shift output buffers and a plurality of charge sharing circuits. The control logic circuit receives input clock pulse signals and a charge sharing signal and acquires voltage level information of each received signal. Each output buffer amplifies a corresponding input clock pulse signal and determines whether to output a signal according to the acquired information of the charge sharing signal. Each charge sharing circuit determines whether to be turned on according to the acquired information of a corresponding input clock pulse signal. When a charge sharing circuit is turned on, the output terminal of a corresponding output buffer and a predetermined voltage level are coupled to each other by the charge sharing circuit, so as to perform the charge sharing operation. Furthermore, a corresponding liquid crystal display device and a corresponding charge sharing method are also provided.

摘要翻译： 电平移位电路包括控制逻辑电路，多个电平移位输出缓冲器和多个电荷共享电路。 控制逻辑电路接收输入时钟脉冲信号和电荷共享信号，并获取每个接收信号的电压电平信息。 每个输出缓冲器放大对应的输入时钟脉冲信号，并根据获取的电荷共享信号的信息确定是否输出信号。 每个电荷共享电路根据所获取的相应输入时钟脉冲信号的信息确定是否被接通。 当电荷共享电路接通时，相应的输出缓冲器的输出端和预定的电压电平通过电荷共享电路彼此耦合，从而进行电荷共享操作。 此外，还提供了相应的液晶显示装置和相应的电荷共享方法。

公开(公告)号：US07750715B2

公开(公告)日：2010-07-06

申请号：US12315189

申请日：2008-11-28

申请人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

发明人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

IPC分类号： G06F1/04

CPC分类号： G09G3/3611 ,  G09G3/3677 ,  G09G2330/023 ,  G11C7/222 ,  G11C19/00 ,  H03K19/0013 ,  H03K19/0016

摘要： A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low.

摘要翻译： 时钟发生电路具有两个输出端，以分别响应于第一和第二输入信号提供第一时钟信号和第二时钟信号。 当第一时钟信号为高电平一段时间时，电荷存储部件用于将一些电荷从第一输出端传送到电荷存储部件，并且当电荷存储部件的电荷从电荷存储部件传送到第二输出端时， 第二个时钟信号为低电平。 在时钟周期的不同时间段，当第二时钟信号为高电平一段时间时，电荷存储部件用于将一些电荷从第二输出端传送到电荷存储部件，并将电荷从 当第一时钟信号为低时，电荷存储部件到第一输出端。

公开(公告)号：US20100134172A1

公开(公告)日：2010-06-03

申请号：US12315189

申请日：2008-11-28

申请人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

发明人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

IPC分类号： G06F1/06

CPC分类号： G09G3/3611 ,  G09G3/3677 ,  G09G2330/023 ,  G11C7/222 ,  G11C19/00 ,  H03K19/0013 ,  H03K19/0016

摘要： A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low.

摘要翻译： 时钟发生电路具有两个输出端，以分别响应于第一和第二输入信号提供第一时钟信号和第二时钟信号。 当第一时钟信号为高电平一段时间时，电荷存储部件用于将一些电荷从第一输出端传送到电荷存储部件，并且当电荷存储部件的电荷从电荷存储部件传送到第二输出端时， 第二个时钟信号为低电平。 在时钟周期的不同时间段，当第二时钟信号为高电平一段时间时，电荷存储部件用于将一些电荷从第二输出端传送到电荷存储部件，并将电荷从 当第一时钟信号为低时，电荷存储部件到第一输出端。