公开(公告)号：US20090108455A1

公开(公告)日：2009-04-30

申请号：US11923194

申请日：2007-10-24

申请人： Charan Gurumurthy ,  Islam Salama ,  Houssam Jomaa ,  Ravi Tanikella

发明人： Charan Gurumurthy ,  Islam Salama ,  Houssam Jomaa ,  Ravi Tanikella

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L21/76879 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.

摘要翻译： 公开了一种用于制造集成电路（IC）的工艺和由此形成的IC。 该方法包括提供基底。 该方法还包括在衬底中形成多个纵向沟槽，并在多个纵向沟槽的至少一个纵向沟槽上沉积第一导电材料层。 第一导电材料层的第一层沉积在第一导电材料的层上。 此后，该方法包括在第二导电材料的第一层上沉积第二导电材料层。 第二导电材料的第二层至少部分地填充至少一个纵向沟槽。 选择第一导电材料使得第一导电材料的还原电位小于第二导电材料的还原电位。

公开(公告)号：US09941158B2

公开(公告)日：2018-04-10

申请号：US13211062

申请日：2011-08-16

申请人： Charan Gurumurthy ,  Islam Salama ,  Houssam Jomaa ,  Ravi Tanikella

发明人： Charan Gurumurthy ,  Islam Salama ,  Houssam Jomaa ,  Ravi Tanikella

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/288

CPC分类号： H01L21/76879 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.

公开(公告)号：US20110298135A1

公开(公告)日：2011-12-08

申请号：US13211062

申请日：2011-08-16

申请人： Charan Gurumurthy ,  Islam Salama ,  Houssam Jomaa ,  Ravi Tanikella

发明人： Charan Gurumurthy ,  Islam Salama ,  Houssam Jomaa ,  Ravi Tanikella

IPC分类号： H01L23/48

CPC分类号： H01L21/76879 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.

摘要翻译： 公开了一种用于制造集成电路（IC）的工艺和由此形成的IC。 该方法包括提供基底。 该方法还包括在衬底中形成多个纵向沟槽，并在多个纵向沟槽的至少一个纵向沟槽上沉积第一导电材料层。 第一导电材料层的第一层沉积在第一导电材料的层上。 此后，该方法包括在第二导电材料的第一层上沉积第二导电材料层。 第二导电材料的第二层至少部分地填充至少一个纵向沟槽。 选择第一导电材料使得第一导电材料的还原电位小于第二导电材料的还原电位。

公开(公告)号：US07998857B2

公开(公告)日：2011-08-16

申请号：US11923194

申请日：2007-10-24

申请人： Charan Gurumurthy ,  Islam Salama ,  Houssam Jomaa ,  Ravi Tanikella

发明人： Charan Gurumurthy ,  Islam Salama ,  Houssam Jomaa ,  Ravi Tanikella

IPC分类号： H01L23/58

CPC分类号： H01L21/76879 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material.

摘要翻译： 公开了一种用于制造集成电路（IC）的工艺和由此形成的IC。 该方法包括提供基底。 该方法还包括在衬底中形成多个纵向沟槽，并在多个纵向沟槽的至少一个纵向沟槽上沉积第一导电材料层。 第一导电材料层的第一层沉积在第一导电材料的层上。 此后，该方法包括在第二导电材料的第一层上沉积第二导电材料层。 第二导电材料的第二层至少部分地填充至少一个纵向沟槽。 选择第一导电材料使得第一导电材料的还原电位小于第二导电材料的还原电位。