公开(公告)号：US20240161817A1

公开(公告)日：2024-05-16

申请号：US17985753

申请日：2022-11-11

申请人： Charles Augustine ,  Seenivasan Subramaniam ,  Patrick Morrow ,  Muhammad M. Khellah

发明人： Charles Augustine ,  Seenivasan Subramaniam ,  Patrick Morrow ,  Muhammad M. Khellah

IPC分类号： G11C11/412 ,  G11C11/419 ,  H01L27/11

CPC分类号： G11C11/412 ,  G11C11/419 ,  H01L27/1104

摘要： Embodiments herein relate to a three-transistor gain cell which is provided using a complementary field-effect transistor device to achieve scaling. The cell includes an n-type layer arranged above a p-type layer. In one implementation, two nMOS transistors are arranged above one pMOS transistor and a conductive path is provided to connect the gate of one of the nMOS transistors to a storage node in the p-type layer, where the storage node is coupled to a drain of the pMOS transistor. In another implementation, one nMOS transistor is arranged above two pMOS transistors and a conductive path is provided to connect the gate of one of the pMOS transistors to a storage node in the n-type layer, where the storage node is coupled to a source of the nMOS transistor.