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公开(公告)号：US20130010815A1
公开(公告)日：2013-01-10
申请号：US13615329
申请日：2012-09-13
申请人： Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian (Alan) Shen , Philip Kruzinski , Guochun (George) Zhao , DeviPrasad Natesan , David R. Jorgensen
发明人： Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian (Alan) Shen , Philip Kruzinski , Guochun (George) Zhao , DeviPrasad Natesan , David R. Jorgensen
IPC分类号： H04J3/06
CPC分类号： H04J3/0682 , H04J3/0667
摘要： An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.
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2.发明授权Apparatus and method of compensating for clock frequency and phase variations by processing packet delay values 有权通过处理分组延迟值来补偿时钟频率和相位变化的装置和方法公开(公告)号：US08031747B2
公开(公告)日：2011-10-04
申请号：US12432630
申请日：2009-04-29
申请人： Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian (Alan) Shen , Philip Kruzinski , Guochun (George) Zhao , DeviPrasad Natesan , David R. Jorgensen
发明人： Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian (Alan) Shen , Philip Kruzinski , Guochun (George) Zhao , DeviPrasad Natesan , David R. Jorgensen
IPC分类号： H04J3/06
CPC分类号： H04J3/0682 , H04J3/0667
摘要： An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.
摘要翻译： 描述了通过处理分组延迟值来补偿电子部件的频率和相位变化的装置和方法。 在一个实施例中，分组延迟确定模块基于与第一和第二电子组件相关联的时间值来确定分组延迟值。 分组延迟选择模块基于第一电子部件的最大频率漂移来选择分组延迟值的子集。 统计参数确定模块基于分组延迟值的子集的部分来评估第一和第二参数。当分组延迟值的子集包括至少两个分组延迟值的最小值时，验证模块验证参数。 如果参数都被验证，则调整模块基于参数补偿第一电子部件的频率变化和相位变化中的至少一个。
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3.发明申请Apparatus and Method of Compensating for Clock Frequency and Phase Variations by Processing Packet Delay Values 有权通过处理分组延迟值补偿时钟频率和相位变化的装置和方法公开(公告)号：US20100278055A1
公开(公告)日：2010-11-04
申请号：US12432630
申请日：2009-04-29
申请人： Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian (Alan) Shen , Philip Kruzinski , Guochun (George) Zhao , DeviPrasad Natesan , David R. Jorgensen
发明人： Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian (Alan) Shen , Philip Kruzinski , Guochun (George) Zhao , DeviPrasad Natesan , David R. Jorgensen
CPC分类号： H04J3/0682 , H04J3/0667
摘要： An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.
摘要翻译： 描述了通过处理分组延迟值来补偿电子部件的频率和相位变化的装置和方法。 在一个实施例中，分组延迟确定模块基于与第一和第二电子组件相关联的时间值来确定分组延迟值。 分组延迟选择模块基于第一电子部件的最大频率漂移来选择分组延迟值的子集。 统计参数确定模块基于分组延迟值的子集的部分来评估第一和第二参数。当分组延迟值的子集包括至少两个分组延迟值的最小值时，验证模块验证参数。 如果参数都被验证，则调整模块基于参数补偿第一电子部件的频率变化和相位变化中的至少一个。
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4.发明授权Apparatus and method of compensating for clock frequency and phase variations by processing packet delay values 有权通过处理分组延迟值来补偿时钟频率和相位变化的装置和方法公开(公告)号：US08494011B2
公开(公告)日：2013-07-23
申请号：US13615329
申请日：2012-09-13
申请人： Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian Alan Shen , Philip Kruzinski , Guochun George Zhao , DeviPrasad Natesan , David R. Jorgensen
发明人： Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian Alan Shen , Philip Kruzinski , Guochun George Zhao , DeviPrasad Natesan , David R. Jorgensen
IPC分类号： H04J3/06
CPC分类号： H04J3/0682 , H04J3/0667
摘要： An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.
摘要翻译： 描述了通过处理分组延迟值来补偿电子部件的频率和相位变化的装置和方法。 在一个实施例中，分组延迟确定模块基于与第一和第二电子组件相关联的时间值来确定分组延迟值。 分组延迟选择模块基于第一电子部件的最大频率漂移来选择分组延迟值的子集。 统计参数确定模块基于分组延迟值的子集的部分来评估第一和第二参数。 验证模块在分组延迟值的子集包括至少两个分组延迟值的最小值的每个部分时验证参数。 如果参数都被验证，则调整模块基于参数补偿第一电子部件的频率变化和相位变化中的至少一个。
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5.发明授权Apparatus and method of compensating for clock frequency and phase variations by processing packet delay values 有权通过处理分组延迟值来补偿时钟频率和相位变化的装置和方法公开(公告)号：US08270438B2
公开(公告)日：2012-09-18
申请号：US13221722
申请日：2011-08-30
申请人： Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian Alan Shen , Philip Kruzinski , Guochun George Zhao , DeviPrasad Natesan , David R. Jorgensen
发明人： Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian Alan Shen , Philip Kruzinski , Guochun George Zhao , DeviPrasad Natesan , David R. Jorgensen
IPC分类号： H04J3/06
CPC分类号： H04J3/0682 , H04J3/0667
摘要： An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.
摘要翻译： 描述了通过处理分组延迟值来补偿电子部件的频率和相位变化的装置和方法。 在一个实施例中，分组延迟确定模块基于与第一和第二电子组件相关联的时间值来确定分组延迟值。 分组延迟选择模块基于第一电子部件的最大频率漂移来选择分组延迟值的子集。 统计参数确定模块基于分组延迟值的子集的部分来评估第一和第二参数。 验证模块在分组延迟值的子集包括至少两个分组延迟值的最小值的每个部分时验证参数。 如果参数都被验证，则调整模块基于参数补偿第一电子部件的频率变化和相位变化中的至少一个。
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6.发明申请APPARATUS AND METHOD OF COMPENSATING FOR CLOCK FREQUENCY AND PHASE VARIATIONS BY PROCESSING PACKET DELAY VALUES 有权通过处理分组延迟值对时钟频率和相位变化进行补偿的装置和方法公开(公告)号：US20110310766A1
公开(公告)日：2011-12-22
申请号：US13221722
申请日：2011-08-30
申请人： Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian (Alan) Shen , Philip Kruzinski , Guochun George Zhao , DeviPrasad Natesan , David R. Jorgensen
发明人： Charles F. Barry , Meenakshi S. Subramanian , Feng Frank Pan , Tian (Alan) Shen , Philip Kruzinski , Guochun George Zhao , DeviPrasad Natesan , David R. Jorgensen
IPC分类号： H04L12/26
CPC分类号： H04J3/0682 , H04J3/0667
摘要： An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.
摘要翻译： 描述了通过处理分组延迟值来补偿电子部件的频率和相位变化的装置和方法。 在一个实施例中，分组延迟确定模块基于与第一和第二电子组件相关联的时间值来确定分组延迟值。 分组延迟选择模块基于第一电子部件的最大频率漂移来选择分组延迟值的子集。 统计参数确定模块基于分组延迟值的子集的部分来评估第一和第二参数。 验证模块在分组延迟值的子集包括至少两个分组延迟值的最小值的每个部分时验证参数。 如果参数都被验证，则调整模块基于参数补偿第一电子部件的频率变化和相位变化中的至少一个。
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7.发明授权Apparatus and method of using spread pulse modulation to increase the control resolution of an electronic device 有权使用扩展脉冲调制以增加电子设备的控制分辨率的装置和方法公开(公告)号：US07443328B2
公开(公告)日：2008-10-28
申请号：US11843504
申请日：2007-08-22
IPC分类号： H03M1/66
CPC分类号： H03M1/66 , H03J7/02 , H03J2200/02 , H03J2200/07
摘要： An apparatus and method are described to increase the control resolution of an electronic device. In one embodiment, the invention includes a spread pulse modulation module to generate a first set of bits based on a second set of bits that is larger than the first set of bits. The spread pulse modulation module modulates the least significant bit (LSB) of the first set of bits based on information including the LSB modulation period and the LSB modulation duty cycle. The spread pulse modulation module also modulates the least significant bit of the first set of bits so that the least significant bit transitions at least twice from a high value to a low value during the modulation period. This embodiment of the invention also includes a digital-to-analog conversion module to generate an analog input signal to the electronic device based on the first set of bits.
摘要翻译： 描述了一种用于增加电子设备的控制分辨率的装置和方法。 在一个实施例中，本发明包括扩展脉冲调制模块，用于基于大于第一组位的第二组位产生第一组位。 扩展脉冲调制模块基于包括LSB调制周期和LSB调制占空比的信息来调制第一组位的最低有效位（LSB）。 扩展脉冲调制模块还调制第一组位的最低有效位，使得最低有效位在调制周期期间从高值至少两次转变为低值。 本发明的该实施例还包括数模转换模块，用于基于第一组位产生到电子设备的模拟输入信号。
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公开(公告)号：US06088360A
公开(公告)日：2000-07-11
申请号：US656558
申请日：1996-05-31
IPC分类号： G06T9/00 , H04N7/32 , H04N21/2365 , H04N21/434 , H04J3/16 , H04N3/22 , H04N7/12
CPC分类号： H04N21/2365 , H04N19/152 , H04N21/4347 , H04N19/50
摘要： A video multiplexer is disclosed which incorporates a dynamic rate control feature. MPEG encoded video signals for each channel are stored in a first-in first-out (FIFO) buffer. A packetizer for each channel detects the level in the FIFO buffer and issues a request signal to the video multiplexer that the channel desires to transmit the video signals on the network. The bandwidth allocation for a channel is either preselected by the video provider or automatically selected, and tokens are issued by a counter associated with each channel to give greater network access to those channels which require a higher bandwidth. A token multiplier detects the bandwidth needs of the various channels by detecting the rate that the FIFO buffer is being filled and automatically multiplies the number of consecutive packets which the packetizer may transmit over the multiplexer during a single grant.
摘要翻译： 公开了一种包含动态速率控制特征的视频多路复用器。 每个通道的MPEG编码视频信号被存储在先进先出（FIFO）缓冲器中。 每个通道的分组器检测FIFO缓冲器中的电平，并向视频多路复用器发出信号期望在网络上传输视频信号的请求信号。 频道的带宽分配由视频提供商预先选择或自动选择，令牌由与每个频道相关的计数器发出，以给予需要更高带宽的那些频道更大的网络访问。 令牌乘法器通过检测FIFO缓冲器被填充的速率来检测各种信道的带宽需求，并且在单个授权期间自动乘以分组器可以通过多路复用器发送的连续分组的数量。
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9.发明授权Apparatus and method of synchronizing distribution of packet services across a distributed network 有权在分布式网络上同步分组业务分发的装置和方法公开(公告)号：US07693130B2
公开(公告)日：2010-04-06
申请号：US11843539
申请日：2007-08-22
IPC分类号： H04J3/06
CPC分类号： H04J3/0632 , H04L12/5692 , H04W36/0011
摘要： An apparatus and method are described for synchronizing distribution of packet information. In one embodiment, the invention includes timestamp processing logic to process a transmit time indicator embedded within the packet information, where the transmit time indicator is based on a time reference, and service synchronization queuing logic to hold the packet information until a time offset after the transmit time indicator, where the service synchronization queuing logic is synchronized to the time reference.
摘要翻译： 描述了用于使分组信息的分发同步的装置和方法。 在一个实施例中，本发明包括时间戳处理逻辑，用于处理嵌入在分组信息内的发送时间指示符，其中发送时间指示符基于时间参考，以及服务同步排队逻辑以保持分组信息，直到在 传输时间指示符，其中服务同步排队逻辑与时间参考同步。
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公开(公告)号：US06865149B1
公开(公告)日：2005-03-08
申请号：US09519442
申请日：2000-03-03
CPC分类号： H04L45/28 , H04L12/42 , H04L45/00 , H04L45/123 , H04L45/22
摘要： The disclosed network includes two rings, wherein a first ring transmits data in a clockwise direction, and the other ring transmits data in a counterclockwise direction. The traffic is removed from the ring by the destination node. During normal operations (i.e., all spans operational), data between nodes flows on the ring that would provide the minimum number of hops to the destination node. Thus, both rings are fully utilized during normal operations. The nodes periodically test the bit error rate of the links (or the error rate is constantly calculated) to detect a fault in one of the links. The detection of such a fault sends a broadcast signal to all nodes to reconfigure a routing table within the node so as to identify the optimum routing of source traffic to the destination node after the fault. Since the available links will now see more data traffic due to the failed link, traffic designated as “unprotected” traffic is given lower priority and may be dropped or delayed in favor of the “protected” traffic. Specific techniques are described for identifying a failed link, communicating the failed link to the other nodes, differentiating between protected and unprotected classes of traffic, and updating the routing tables.
摘要翻译： 所公开的网络包括两个环，其中第一环以顺时针方向传输数据，另一个环以逆时针方向发送数据。 目的节点将流量从环中移除。 在正常操作期间（即所有跨度可操作），节点之间的数据在环上流动，将向目标节点提供最小跳数。 因此，在正常操作期间两个环都被充分利用。 节点周期性地测试链路的误码率（或者不断地计算错误率）以检测链路之一的故障。 这种故障的检测向所有节点发送广播信号，以重新配置节点内的路由表，以便在故障之后识别到源目的地节点的源业务的最佳路由。 由于可用的链接现在将看到由于链路故障导致的更多的数据流量，所以指定为“未受保护”流量的流量被给予较低优先级，并且可能会被丢弃或延迟，有利于“受保护”流量。 描述用于识别故障链路，将故障链路传递到其他节点，区分受保护和不受保护的流量类别以及更新路由表的特定技术。
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