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1.发明授权Processor with coherent bus controller at perpendicularly intersecting axial bus layout for communication among SMP compute elements and off-chip I/O elements 有权具有相干总线控制器的处理器，用于垂直相交的轴向总线布局，用于SMP计算元件和片外I / O元件之间的通信公开(公告)号：US07865650B2
公开(公告)日：2011-01-04
申请号：US12060670
申请日：2008-04-01
IPC分类号： G06F13/14
CPC分类号： H01L27/0207 , H01L27/11898
摘要： A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of the processor chip. The I/O interfaces may be distributed uniformly along portions of the perimeter.
摘要翻译： 对称多处理（SMP）处理器包括用于在沿着主互连干线位于多个计算单元之间进行信息通信的主互连干线。 处理器还包括可相对于主互连干线垂直定向的次级互连干线。 辅助互连中继线通过处理器芯片周边的多个I / O接口来传送芯片外的信息。 I / O接口可以沿周边的部分均匀分布。
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2.发明申请Information Handling System Including Multiple Compute Element Processor With Primary And Secondary Interconnect Trunks 有权包括具有主要和次要互连中继线的多个计算元件处理器的信息处理系统公开(公告)号：US20090248946A1
公开(公告)日：2009-10-01
申请号：US12060670
申请日：2008-04-01
IPC分类号： G06F13/00
CPC分类号： H01L27/0207 , H01L27/11898
摘要： A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of the processor chip. The I/O interfaces may be distributed uniformly along portions of the perimeter.
摘要翻译： 对称多处理（SMP）处理器包括用于在沿着主互连干线位于多个计算单元之间进行信息通信的主互连干线。 处理器还包括可相对于主互连干线垂直定向的次级互连干线。 辅助互连中继线通过处理器芯片周边的多个I / O接口来传送芯片外的信息。 I / O接口可以沿周边的部分均匀分布。
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