利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

2 条记录 (耗时 0.024 秒)

    Processor chip with multiple computing elements and external i/o interfaces connected to perpendicular interconnection trunks communicating coherency signals via intersection bus controller
    1.
    发明授权
    Processor chip with multiple computing elements and external i/o interfaces connected to perpendicular interconnection trunks communicating coherency signals via intersection bus controller 有权
    具有多个计算元件的处理器芯片和连接到垂直互连干线的外部I / O接口，通过交叉点总线控制器通信相干信号

    公开(公告)号：US07917730B2

    公开(公告)日：2011-03-29

    申请号：US12060683

    申请日：2008-04-01

    申请人： Charles Francis Marino ,  John Thomas Holloway, Jr. ,  Praveen S. Reddy ,  William John Starke

    发明人： Charles Francis Marino ,  John Thomas Holloway, Jr. ,  Praveen S. Reddy ,  William John Starke

    IPC分类号： G06F13/40

    CPC分类号： G06F15/8007

    摘要： A multi-chip processor apparatus includes multiple processor chips on a substrate. At least one of the multiple processor chips includes a die with a primary interconnect trunk that communicates information between multiple compute elements situated along the primary interconnect trunk. That multiple processor chip includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of that multiple processor chip. The secondary interconnect trunk intersects the primary interconnect trunk at an intersection at which a bus control element is located. The bus control element includes a primary trunk interface that couples to the primary interconnect trunk at the intersection to enable the bus control element to control on-chip communication among the compute elements via coherency signals on the primary interconnect trunk. The bus control element includes a secondary trunk interface coupled to the secondary interconnect trunk.

    摘要翻译： 多芯片处理器装置在基板上包括多个处理器芯片。 多个处理器芯片中的至少一个包括具有主互连干线的管芯，其在沿着主互连干线位于的多个计算元件之间传送信息。 该多处理器芯片包括可相对于主互连干线垂直定向的次级互连干线。 辅助互连中继线通过多处理器芯片周边的多个I / O接口来传送芯片外的信息。 次互连干线在总线控制元件所在的交点处与主互连干线相交。 总线控制元件包括在交叉点处耦合到主互连干线的主干接口，以使得总线控制元件能够通过主互连干线上的相干信号来控制计算元件之间的片上通信。 总线控制元件包括耦合到辅助互连主干的辅助中继接口。