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1.发明授权Apparatus to use fabric initialization to test functionality of all inter-chip paths between processors in system 失效使用结构初始化来测试系统中处理器之间的所有芯片间路径的功能的装置公开(公告)号：US07873861B2
公开(公告)日：2011-01-18
申请号：US12163885
申请日：2008-06-27
IPC分类号： G06F11/00
CPC分类号： G06F11/2242
摘要： A method, apparatus, and program for systematically testing the functionality of all connections in a multi-tiered bus system that connects a large number of processors. Each bus controller is instructed to send a test version of a snoop request to all of the other processors and to wait for the replies. If a connection is bad, the port associated with that connection will time out. Detection of a time-out will cause the initialization process to be halted until the problem can be isolated and resolved.
摘要翻译： 一种用于系统地测试连接大量处理器的多层总线系统中所有连接的功能的方法，装置和程序。 指示每个总线控制器向所有其他处理器发送窥探请求的测试版本，并等待回复。 如果连接不良，与该连接关联的端口将超时。 检测超时将导致初始化过程停止，直到问题被隔离和解决为止。
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2.发明授权Data processing system, method and interconnect fabric supporting multiple planes of processing nodes 有权支持多个处理节点平面的数据处理系统，方法和互连结构公开(公告)号：US07818388B2
公开(公告)日：2010-10-19
申请号：US11245887
申请日：2005-10-07
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A data processing system includes a first plane including a first plurality of processing nodes, each including multiple processing units, and a second plane including a second plurality of processing nodes, each including multiple processing units. The data processing system also includes a plurality of point-to-point first tier links. Each of the first plurality and second plurality of processing nodes includes one or more first tier links among the plurality of first tier links, where the first tier link(s) within each processing node connect a pair of processing units in the same processing node for communication. The data processing system further includes a plurality of point-to-point second tier links. At least a first of the plurality of second tier links connects processing units in different ones of the first plurality of processing nodes, at least a second of the plurality of second tier links connects processing units in different ones of the second plurality of processing nodes, and at least a third of the plurality of second tier links connects a processing unit in the first plane to a processing unit in the second plane.
摘要翻译： 数据处理系统包括包括第一多个处理节点的第一平面，每个处理节点包括多个处理单元，以及包括第二多个处理节点的第二平面，每个处理节点包括多个处理单元。 数据处理系统还包括多个点对点第一层链路。 第一多个处理节点和第二多个处理节点中的每一个包括多个第一层链路之中的一个或多个第一层链路，其中每个处理节点内的第一层链路连接相同处理节点中的一对处理单元，用于 通讯。 数据处理系统还包括多个点到点第二层链路。 所述多个第二层链路中的至少第一层连接所述第一多个处理节点中的不同处理节点中的处理单元，所述多个第二层链路中的至少一个链接连接所述第二多个处理节点中的不同处理节点中的处理单元， 并且所述多个第二层链路中的至少三分之一链路将所述第一平面中的处理单元连接到所述第二平面中的处理单元。
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3.发明授权Request and combined response broadcasting to processors coupled to other processors within node and coupled to respective processors in another node 失效向耦合到节点内的其他处理器并耦合到另一节点中的相应处理器的处理器的请求和组合响应广播公开(公告)号：US07627738B2
公开(公告)日：2009-12-01
申请号：US11960283
申请日：2007-12-19
IPC分类号： G06F15/163
CPC分类号： G06F15/17337
摘要： A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. Each of the plurality of first processing units is coupled to a respective one of the plurality of second processing units in the second processing node by a respective one of a plurality of point-to-point links.
摘要翻译： 数据处理系统包括第一处理节点和第二处理节点。 第一处理节点包括彼此耦合以进行通信的多个第一处理单元，并且第二处理节点包括彼此耦合以进行通信的多个第二处理单元。 多个第一处理单元中的每个通过多个点对点链接中的相应一个耦合到第二处理节点中的多个第二处理单元中的相应一个。
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4.发明授权Method to use fabric initialization to test functionality of all inter-chip paths between processors in system 失效使用结构初始化测试系统中处理器之间所有芯片间路径功能的方法公开(公告)号：US07430684B2
公开(公告)日：2008-09-30
申请号：US11054275
申请日：2005-02-09
IPC分类号： G06F11/00
CPC分类号： G06F11/2242
摘要： A method, apparatus, and program for systematically testing the functionality of all connections in a multi-tiered bus system that connects a large number of processors. Each bus controller is instructed to send a test version of a snoop request to all of the other processors and to wait for the replies. If a connection is bad, the port associated with that connection will time out. Detection of a time-out will cause the initialization process to be halted until the problem can be isolated and resolved.
摘要翻译： 一种用于系统地测试连接大量处理器的多层总线系统中所有连接的功能的方法，装置和程序。 指示每个总线控制器向所有其他处理器发送窥探请求的测试版本，并等待回复。 如果连接不良，与该连接关联的端口将超时。 检测超时将导致初始化过程停止，直到问题被隔离和解决为止。
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5.发明授权Data processing system, method and interconnect fabric having an address-based launch governor 失效具有基于地址的发射调速器的数据处理系统，方法和互连结构公开(公告)号：US07415030B2
公开(公告)日：2008-08-19
申请号：US11054910
申请日：2005-02-10
IPC分类号： H04L12/28
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813 , G06F12/0851
摘要： A data processing system includes an interconnect fabric, a protected resource having a plurality of banks each associated with a respective one of a plurality of address sets, a snooper that controls access to the resource, one or more masters that initiate requests, and interconnect logic coupled to the one or more masters and to the interconnect fabric. The interconnect logic regulates a rate of delivery to the snooper via the interconnect fabric of requests that target any one the plurality of banks of the protected resource.
摘要翻译： 数据处理系统包括互连结构，受保护资源具有多个存储体，每个存储体各自与多个地址集合中的相应一个地址集相关联，控制对资源的访问的监听器，发起请求的一个或多个主站和互连逻辑 耦合到一个或多个主器件和互连结构。 互连逻辑通过针对受保护资源的多个组中的任一个的请求的互连结构来调节到窥探者的传送速率。
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公开(公告)号：US07085847B2
公开(公告)日：2006-08-01
申请号：US10072075
申请日：2002-02-08
IPC分类号： G06F15/16
CPC分类号： H04L12/423 , H04L12/433
摘要： An apparatus for scheduling transmission of a plurality of frames in a network having a plurality of nodes, each frame identified by a type designation, includes a schedule memory and a sequencer. The schedule memory stores a transmission time for each frame type and a list of frames to be transmitted. The sequencer is operable to access the schedule memory and initiate transmission of the frames in the list.
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7.发明授权System for dynamically selecting maximum number of accessible banks of memory per cycle by monitoring actual power to each of the banks to determine the number of accessible banks 失效用于通过监测每个银行的实际功率来确定可访问银行的数量来动态地选择每个周期的可访问存储体的最大数量的系统公开(公告)号：US06539487B1
公开(公告)日：2003-03-25
申请号：US09436958
申请日：1999-11-09
IPC分类号： G06F126
CPC分类号： G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： A method and system for dynamically selecting accessible banks of memory per cycle within a banked cache memory. In accordance with the method and system of the present invention, the application of power to each bank of memory of a banked cache memory is monitored in order to determine a maximum number of selectable bank accesses per cycle such that power application to each of the banks of memory is not degraded. No more than the maximum number of selectable bank accesses per cycle are permitted for subsequent cycles from among the banks of memory, such that the number of accessible banks of memory of a banked cache memory is dynamically selectable to maximize bank accesses per cycle while maintaining an acceptable power application to each of the banks of memory.
摘要翻译： 一种方法和系统，用于在每个周期内动态地选择可存储的存储体组。 根据本发明的方法和系统，监视向每个周期的每个存储体存储器的每个存储体的应用电力，以便确定每个周期的可选择的存储体访问的最大数目，以使每个存储体的电力应用 的内存不降级。 每个周期的可选择的存储体访问的最大数量被允许用于存储器存储器中的后续周期，使得可以动态地选择存储的高速缓冲存储器的存取存储器的数量，以便每个周期最大化存储体存取，同时维持 可接受的电力应用到每个存储器组。
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8.发明授权Method and apparatus for accessing banked embedded dynamic random access memory devices 有权用于访问嵌入式嵌入式动态随机存取存储器件的方法和装置公开(公告)号：US06606680B2
公开(公告)日：2003-08-12
申请号：US09895224
申请日：2001-06-29
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy , William John Starke
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy , William John Starke
IPC分类号： G06F1202
CPC分类号： G06F12/0897 , G11C7/22 , G11C11/408 , G11C2207/104
摘要： An apparatus for accessing a banked embedded dynamic random access memory device is disclosed. The apparatus for accessing a banked embedded dynamic random access memory (DRAM) device comprises a general functional control logic and a bank RAS controller. The general functional control logic is coupled to each bank of the banked embedded DRAM device. Coupled to the general functional control logic, the bank RAS controller includes a rotating shift register having multiple bits. Each bit within the rotating shift register corresponds to each bank of the banked embedded DRAM device. As such, a first value within a bit of the rotating shift register allows accesses to an associated bank of the banked embedded DRAM device, and a second value within a bit of the rotating shift register denies accesses to an associated bank of the banked embedded DRAM device.
摘要翻译： 公开了一种用于访问嵌入式动态随机存取存储器件的装置。 用于访问堆叠式嵌入式动态随机存取存储器（DRAM）装置的装置包括通用功能控制逻辑和银行RAS控制器。 一般的功能控制逻辑耦合到组合的嵌入式DRAM设备的每个组。 耦合到一般功能控制逻辑，银行RAS控制器包括具有多个位的旋转移位寄存器。 旋转移位寄存器内的每个位对应于组合嵌入式DRAM器件的每一组。 这样，旋转移位寄存器的一位内的第一值允许访问分组的嵌入式DRAM设备的相关联的存储体，并且旋转移位寄存器的一位内的第二值拒绝对相关联的组的嵌入式DRAM 设备。
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9.发明授权Method and apparatus for concurrently communicating with multiple embedded dynamic random access memory devices 有权用于与多个嵌入式动态随机存取存储器件同时通信的方法和装置公开(公告)号：US06574719B2
公开(公告)日：2003-06-03
申请号：US09903720
申请日：2001-07-12
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy , William John Starke
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F13/28 , G06F13/4243
摘要： An apparatus for providing concurrent communications between multiple memory devices and a processor is disclosed. Each of the memory device includes a driver, a phase/cycle adjust sensing circuit, and a bus alignment communication logic. Each phase/cycle adjust sensing circuit detects an occurrence of a cycle adjustment from a corresponding driver within a memory device. If an occurrence of a cycle adjustment has been detected, the bus alignment communication logic communicates the occurrence of a cycle adjustment to the processor. The bus alignment communication logic also communicates the occurrence of a cycle adjustment to the bus alignment communication logic in the other memory devices. There are multiple receivers within the processor, and each of the receivers is designed to receive data from a respective driver in a memory device. Each of the receivers includes a cycle delay block. The receiver that had received the occurrence of a cycle adjustment informs the other receivers that did not receive the occurrence of a cycle adjustment to use their cycle delay block to delay the incoming data for at least one cycle.
摘要翻译： 公开了一种用于在多个存储器件和处理器之间提供并发通信的装置。 每个存储器件包括驱动器，相位/周期调整感测电路和总线对准通信逻辑。 每个相位/周期调整感测电路检测来自存储器件内相应的驱动器的周期调整的发生。 如果已经检测到循环调整的发生，则总线对准通信逻辑将处理器的循环调整的发生传达给处理器。 总线对准通信逻辑还将循环调整的发生与其他存储器件中的总线对准通信逻辑进行通信。 处理器内有多个接收器，并且每个接收器被设计成从存储器设备中的相应驱动器接收数据。 每个接收器包括循环延迟块。 接收到发生循环调整的接收器通知其他接收机没有接收周期调整的发生，以使用它们的周期延迟块来延迟输入数据至少一个周期。
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10.发明授权Method and apparatus for forwarding data in a hierarchial cache memory architecture 失效用于在分层缓存存储器架构中转发数据的方法和装置公开(公告)号：US06467030B1
公开(公告)日：2002-10-15
申请号：US09435962
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy
IPC分类号： G06F1200
CPC分类号： G06F12/0897 , G06F12/0862 , G06F2212/6022
摘要： A method and apparatus for forwarding data in a hierarchial cache memory architecture is disclosed. A cache memory hierarchy includes multiple levels of cache memories, each level having a different size and speed. A command is initially issued from a processor to the cache memory hierarchy. If the command is a Demand Load command, data corresponding to the Demand Load command is immediately forwarded from a cache having the data to the processor. Otherwise, if the command is a Prefetch Load command, data corresponding to the Prefetch Load command is held in a cache reload buffer within a cache memory preceding the processor.
摘要翻译： 公开了一种用于在分级高速缓冲存储器架构中转发数据的方法和装置。 高速缓冲存储器层级包括多级缓存存储器，每级具有不同的大小和速度。 命令最初从处理器发出到高速缓存存储器层次结构。 如果命令是Demand Load命令，则与Demand Load命令相对应的数据将立即从具有数据的缓存转发到处理器。 否则，如果命令是预取加载命令，则与预取加载命令对应的数据保存在处理器之前的高速缓存中的缓存重新加载缓冲区中。
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