公开(公告)号：US20130326455A1

公开(公告)日：2013-12-05

申请号：US13485828

申请日：2012-05-31

申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Chin Ngai Sze ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Chin Ngai Sze ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5068 ,  G06F17/5081

摘要： An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.

摘要翻译： 改进的电路设计系统可以包括计算机处理器，以通过物理合成来执行电路的放置。 该系统还可以包括控制器，用于计算电路的至少一个选定元件的优选位置，并且计算每个选定元件的放置约束。 该系统可以进一步包括通过用放置约束执行另一轮物理合成而产生的电路的更新设计。

公开(公告)号：US09524363B2

公开(公告)日：2016-12-20

申请号：US13485828

申请日：2012-05-31

申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Chin Ngai Sze ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Chin Ngai Sze ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5068 ,  G06F17/5081

摘要： An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.

摘要翻译： 改进的电路设计系统可以包括计算机处理器，以通过物理合成来执行电路的放置。 该系统还可以包括控制器，用于计算电路的至少一个选定元件的优选位置，并且计算每个选定元件的放置约束。 该系统可以进一步包括通过用放置约束执行另一轮物理合成而产生的电路的更新设计。

公开(公告)号：US20120124539A1

公开(公告)日：2012-05-17

申请号：US12947445

申请日：2010-11-16

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.

摘要翻译： 提供了一种用于通过本地时钟缓冲器控制优化进行码头优化的物理综合工具。 物理合成流程包括延迟时钟路由的曝光，直到时钟优化放置阶段为止。 物理综合工具克隆了第一个本地时钟缓冲区。 然后，物理综合工具对整个设计运行时序分析，以计算这一必然破坏性步骤的影响。 在克隆本地时钟缓冲器之后，物理综合工具增加了一个额外的优化步骤来对驱动本地时钟缓冲器的控制信号进行目标。 该优化步骤可以包括锁存克隆，定时驱动放置，缓冲器插入和重新供电。 该流程减轻了高扇出网络，并显着提高了进入时钟优化布局的时间。 放置后，物理综合工具将锁存器和本地时钟缓冲器固定到位，插入时钟路由并释放本地时钟缓冲区。

公开(公告)号：US08418108B2

公开(公告)日：2013-04-09

申请号：US13162806

申请日：2011-06-17

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan ,  Brian C. Wilson

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan ,  Brian C. Wilson

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031 ,  G06F2217/84

摘要： The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.

摘要翻译： 通过将默认转换速率分配给先前逻辑级的输出门，该值大于设计的中间转换速率来计算集成电路设计选定门的输入。 该默认转换速率通过逻辑级传播，以在所选择的门产生输入转换速率。 默认转换速率对应于应用于设计中随机选择的门的初步压摆率的有限样本的预定百分位数。 作为第二逻辑级中从输出门到第一门的线长度的已知特性的函数调整默认转换速率。 基于输入转换速率来计算所选择的门的延迟。 输入转换速率可以在一次优化迭代期间存储，并在以后的优化迭代中用作默认转换速率。

公开(公告)号：US20120324409A1

公开(公告)日：2012-12-20

申请号：US13162806

申请日：2011-06-17

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan ,  Brian C. Wilson

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan ,  Brian C. Wilson

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5031 ,  G06F2217/84

摘要： The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration.

摘要翻译： 通过将默认转换速率分配给先前逻辑级的输出门，该值大于设计的中间转换速率来计算集成电路设计选定门的输入。 该默认转换速率通过逻辑级传播，以在所选择的门产生输入转换速率。 默认转换速率对应于应用于设计中随机选择的门的初步压摆率的有限样本的预定百分位数。 作为第二逻辑级中从输出门到第一门的线长度已知特性的函数调整默认转换速率。 基于输入转换速率来计算所选择的门的延迟。 输入转换速率可以在一次优化迭代期间存储，并在以后的优化迭代中用作默认转换速率。

公开(公告)号：US08667441B2

公开(公告)日：2014-03-04

申请号：US12947445

申请日：2010-11-16

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.

摘要翻译： 提供了一种用于通过本地时钟缓冲器控制优化进行码头优化的物理综合工具。 物理合成流程包括延迟时钟路由的曝光，直到时钟优化放置阶段为止。 物理综合工具克隆了第一个本地时钟缓冲区。 然后，物理综合工具对整个设计运行时序分析，以计算这一必然破坏性步骤的影响。 在克隆本地时钟缓冲器之后，物理综合工具增加了一个额外的优化步骤来对驱动本地时钟缓冲器的控制信号进行目标。 该优化步骤可以包括锁存克隆，定时驱动放置，缓冲器插入和重新供电。 该流程减轻了高扇出网络，并显着提高了进入时钟优化布局的时间。 放置后，物理综合工具将锁存器和本地时钟缓冲器固定到位，插入时钟路由并释放本地时钟缓冲区。

公开(公告)号：US20080282213A1

公开(公告)日：2008-11-13

申请号：US12181447

申请日：2008-07-29

申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.

摘要翻译： 提出了一种强制定向布置程序的方法。 该方法包括：将多个对象从小区网表分配给分组; 基于箱子移动物体; 基于所述移动来计算所述多个对象中的每个对象的扩展力的大小; 基于物体的展开力的大小对物体进行分类; 基于指示基于位置拥塞的最高百分比，阈值力和阈值中的至少一个的阈值来选择排序对象的子集; 将所选择的物体的展开力调整为等于表示最小铺展力的预定值; 以及基于所选择的对象的调整的展开力确定所述对象的位置。

公开(公告)号：US20110302545A1

公开(公告)日：2011-12-08

申请号：US12796501

申请日：2010-06-08

申请人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Andrew D. Huber ,  Zhuo Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Jarrod A. Roy ,  Taraneh Taghavi ,  Gustavo E. Tellez ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.

摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块，其中某些图块具有单元格。 扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。 扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。 扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。 扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

公开(公告)号：US07882475B2

公开(公告)日：2011-02-01

申请号：US12181447

申请日：2008-07-29

申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5072

摘要： A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.

摘要翻译： 提出了一种强制定向布置程序的方法。 该方法包括：将多个对象从小区网表分配给分组; 基于箱子移动物体; 基于所述移动来计算所述多个对象中的每个对象的扩展力的大小; 基于物体的展开力的大小对物体进行分类; 基于指示基于位置拥塞的最高百分比，阈值力和阈值中的至少一个的阈值来选择排序对象的子集; 将所选择的物体的展开力调整为等于表示最小铺展力的预定值; 以及基于所选择的对象的调整的展开力确定所述对象的位置。

公开(公告)号：US08495534B2

公开(公告)日：2013-07-23

申请号：US12796550

申请日：2010-06-08

申请人： Charles J. Alpert ,  Zhuo D. Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo D. Li ,  Gi-Joon Nam ,  Shyam Ramji ,  Lakshmi N. Reddy ,  Jarrod A. Roy ,  Taraneh E. Taghavi ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells.

摘要翻译： 一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。 扩展器将单元格分配给图块。 扩展器确定高度详细的路由成本瓦片类，其中高详细路由成本瓦片类是具有高详细路由成本的一类瓦片。 扩展器选择高详细路由代价块类别的块内的单元，以在所选择的块中形成选定的单元。 扩展器应用多种技术在新位置重新定位这些单元，以提高详细的可布线性。 扩展器可以在所选择的单元周围放置扩展的边界框，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片，并且在边界框内重新定位所选择的单元以形成修改的设计以改进详细的可布线性。 扩张器也可能使这些细胞膨胀并合法化。