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公开(公告)号：US5548719A
公开(公告)日：1996-08-20
申请号：US422742
申请日：1995-04-14
CPC分类号： G06F11/3466 , G06F11/25 , G06F11/321
摘要： A system and method for analyzing large logic traces, with the system having an input for regular expressions, a generator for receiving the regular expressions and generating finite automata which use arithmetic/logic expressions that permit the use of a substantially infinite alphabet, an input for a large trace array, and an analyzer for searching the large trace array with the finite automata, with the analyzer producing results of the search.
摘要翻译： 一种用于分析大逻辑轨迹的系统和方法，系统具有用于正则表达式的输入，用于接收正则表达式的生成器，并且生成使用允许使用基本无限字母表的算术/逻辑表达式的有限自动机，输入 一个大的跟踪阵列，以及一个用有限自动机搜索大轨迹的分析仪，分析仪产生搜索结果。
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公开(公告)号：US5228066A
公开(公告)日：1993-07-13
申请号：US871938
申请日：1992-04-22
申请人： Charles J. DeVane
发明人： Charles J. DeVane
CPC分类号： G06F11/3419 , G01P3/489 , G06F1/14 , G06F11/348 , G06F2201/88
摘要： A circuit that may be implemented in a computer system that will measure the maximum and minimum time intervals for system elements to respond to a request for data or information. The circuit includes control logic that controls operation of the circuit, an up-counter and a down-counter that are used together for measuring the maximum or minimum response time interval, and a display for displaying the maximum or minimum response time interval that is measured during a test period.
摘要翻译： 可以在计算机系统中实现的电路，该电路将测量系统元件响应数据或信息请求的最大和最小时间间隔。 该电路包括控制电路操作的控制逻辑，用于一起用于测量最大或最小响应时间间隔的上计数器和递减计数器以及用于显示被测量的最大或最小响应时间间隔的显示器 在测试期间。
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公开(公告)号：US07523443B2
公开(公告)日：2009-04-21
申请号：US10414250
申请日：2003-04-15
申请人： Charles J. DeVane
发明人： Charles J. DeVane
摘要： A programming language type system includes, in a memory, a set of numeric type including integer types, fixed-point types and floating-point types, a set of type propagation rules to automatically determine result types of any combination of integer types, fixed-point types and floating-point types, constant annotations to explicitly specify a result type of a literal constant, context-sensitive constants whose type is determined from a context of a constant according to the set of type propagation rules, an assignment operator to explicitly specify a type of a value or computation, and operator annotations to explicitly specify a result type of a computation.
摘要翻译： 一种编程语言类型系统在存储器中包括一组数字类型，包括整数类型，定点类型和浮点类型，一组类型传播规则，用于自动确定整数类型的任何组合的结果类型， 点类型和浮点类型，常量注释以明确指定文字常量的结果类型，上下文相关常数，其类型根据类型传播规则集合的常量的上下文确定，明确指定的分配运算符 一种值或计算的类型，以及明确指定计算结果类型的操作符注释。
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4.发明授权System and method for analyzing complex sequences in trace arrays using multiple finite automata 失效使用多个有限自动机分析跟踪数组中的复杂序列的系统和方法
公开(公告)号：US5299206A
公开(公告)日：1994-03-29
申请号：US781889
申请日：1991-10-24
CPC分类号： G06F11/25
摘要： A system and method for analyzing complex overlapping sequences of events in trace arrays, with the system having an input for receiving regular expressions that have been grouped in a predetermined manner, a generator for receiving the grouped regular expressions and generating multiple finite automata based on the groupings of regular expressions, with each finite automaton being generated using arithmetic/logic expressions to permit the use of a substantially infinite alphabet, an input for the trace array, and an analyzer for searching the trace array simultaneously with the multiple finite automata and providing a way by which the multiple finite automata may communicate with one another during searching, with the analyzer further outputting the results of the search.
摘要翻译： 一种用于分析跟踪阵列中的复杂重叠事件序列的系统和方法，系统具有用于接收以预定方式分组的正则表达式的输入，用于接收分组的正则表达式并基于 正则表达式的分组，其中使用算术/逻辑表达式生成每个有限自动机，以允许使用基本上无限的字母表，跟踪数组的输入，以及用于与多个有限自动机同时搜索跟踪数组的分析器，并提供一个 多重有限自动机在搜索期间可以彼此通信的方式，分析器进一步输出搜索结果。
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公开(公告)号：US5187676A
公开(公告)日：1993-02-16
申请号：US724531
申请日：1991-06-28
申请人： Charles J. DeVane
发明人： Charles J. DeVane
IPC分类号： G06F7/58
CPC分类号： G06F7/586
摘要： A high-speed pseudo-random number generator comprising a first shift register with p stages for storing and shifting a value with the least significant bit being adjacent an output terminal; a second shift register with b stages for storing and shifting a pre-loaded value with the least significant bit of the pre-loaded value being stored in the bth stage; a serial adder having at least l input taps with the serial adder adding the two values shifted out of the first and second shift registers and loading the sum output of the serial adder into the first shift register; and a controller for controlling clocking of the first and second shift registers and the serial adder, controlling pre-loading of the pre-load value into the second shift register, and clearing the serial adder.
摘要翻译： 一种高速伪随机数发生器，包括具有p级的第一移位寄存器，用于存储和移位最低有效位邻近输出端的值; 第二移位寄存器，其具有用于存储和移位预载值的第二移位寄存器，其中所述预加载值的最低有效位被存储在第b级中; 串行加法器具有至少一个输入抽头，串行加法器将从第一和第二移位寄存器移出的两个值相加，并将串行加法器的和输出加载到第一移位寄存器中; 以及用于控制第一和第二移位寄存器和串行加法器的时钟的控制器，控制预加载值预加载到第二移位寄存器中，以及清除串行加法器。
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