公开(公告)号：US06401234B1

公开(公告)日：2002-06-04

申请号：US09465294

申请日：1999-12-17

申请人： Charles Jay Alpert ,  Rama Gopal Gandham ,  Jiang Hu ,  Jose Luis Neves ,  Stephen Thomas Quay

发明人： Charles Jay Alpert ,  Rama Gopal Gandham ,  Jiang Hu ,  Jose Luis Neves ,  Stephen Thomas Quay

IPC分类号： G06F1750

CPC分类号： G06F17/5077

摘要： A method and system for re-routing interconnects within an integrated circuit design having blockages and bays is disclosed. A net within the integrated circuit design is initially decomposed into multiple two-paths. The net includes interconnects previously routed by utilizing a Steiner tree routing algorithm. Next, a cost associated with each of the two-paths is calculated. A two-path having a a high cost is subsequently selected and re-routed with a lower cost two-path.

摘要翻译： 公开了一种用于在具有阻塞和间隔的集成电路设计中重新路由互连的方法和系统。 集成电路设计中的网络最初分解成多个双向路径。 网络包括先前通过利用Steiner树路由算法路由的互连。 接下来，计算与每个双向路径相关联的成本。 随后选择具有高成本的双路径并以较低成本的双路径重新路由。

公开(公告)号：US20090106709A1

公开(公告)日：2009-04-23

申请号：US11873919

申请日：2007-10-17

申请人： Christopher Carney ,  Jose Luis Neves ,  Biagio Pluchino

发明人： Christopher Carney ,  Jose Luis Neves ,  Biagio Pluchino

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505

摘要： A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an interface in communication with the logic circuit analyzer to select a target slack-value for each one of the plurality of nets. The logic circuit analyzer may determine a slack-value for each net. In addition, the logic circuit analyzer may selectively reduce resistive-capacitive delay for each net respectively if the determined slack-value is less than the target slack-value for each respective net.

摘要翻译： 用于改进逻辑电路的系统可以包括处理器和与处理器通信以对多个网络建模的逻辑电路分析器。 该系统还可以包括与逻辑电路分析器通信的接口，以针对多个网络中的每一个网络选择目标松弛值。 逻辑电路分析器可以确定每个网络的松弛值。 此外，如果确定的松弛值小于每个相应网的目标松弛值，则逻辑电路分析器可以分别选择性地减小每个网络的电阻 - 电容延迟。

公开(公告)号：US20050108665A1

公开(公告)日：2005-05-19

申请号：US10716772

申请日：2003-11-19

申请人： Jose Luis Neves ,  Jiyoun Kim

发明人： Jose Luis Neves ,  Jiyoun Kim

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/505

摘要： A method is provided to speed up timing optimization after placement by parallelizing the optimization step. The method includes performing multiple partitions in the set of timing critical paths such that each partition can be optimized independently in a separate processor. To eliminate the need for inter-processor communication, conditions of timing independence and physical independence are imposed on each partition, thereby defining sub-sets of endpoints and paths associated therewith. The optimizing is performed in parallel by the processors, each of the processors optimizing timing of the paths associated with the endpoints in respective sub-sets. In a preferred embodiment, an endpoint graph is constructed from the list of critical paths, where the endpoint graph has at least one vertex representing critical paths associated with a given endpoint. The partitioning step then includes the step of partitioning the endpoint graph to define sub-sets of vertices.

摘要翻译： 提供了一种通过并行优化步骤来加速放置后的定时优化的方法。 该方法包括在所述一组定时关键路径中执行多个分区，使得可以在单独的处理器中独立地优化每个分区。 为了消除对处理器间通信的需要，对每个分区施加时序独立性和物理独立性的条件，从而定义与其相关联的端点和路径的子集。 优化由处理器并行执行，每个处理器优化与相应子集中的端点相关联的路径的定时。 在优选实施例中，从关键路径列表构建端点图，其中端点图具有表示与给定端点相关联的关键路径的至少一个顶点。 然后，分割步骤包括分割端点图以定义顶点的子集的步骤。