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    CAPACITANCE EXTRACTION FOR ADVANCED DEVICE TECHNOLOGIES
    1.
    发明申请
    CAPACITANCE EXTRACTION FOR ADVANCED DEVICE TECHNOLOGIES 有权
    高级设备技术的电容提取

    公开(公告)号：US20130191798A1

    公开(公告)日：2013-07-25

    申请号：US13357544

    申请日：2012-01-24

    申请人： Arthur Nieuwoudt ,  Jiyoun Kim ,  Mathew Koshy ,  Baribrata Biswas

    发明人： Arthur Nieuwoudt ,  Jiyoun Kim ,  Mathew Koshy ,  Baribrata Biswas

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5036

    摘要： A technology specific information to design the integrated circuit is received. A plurality of canonical hierarchical models to capture an integrated circuit capacitance are created. The plurality of canonical hierarchical models includes at least a canonical model to capture a capacitance of a device having a plurality of conductors, and a canonical model to capture a capacitance between at least a portion of the device and one or more other conductors of the integrated circuit. The canonical hierarchical models can be applied to a layout of the integrated circuit. A capacitance for the layout can be determined based on the canonical hierarchical models.

    摘要翻译： 接收到设计集成电路的技术特定信息。 创建了用于捕获集成电路电容的多个规范层次模型。 多个规范层级模型至少包括一个规范模型，用于捕获具有多个导体的装置的电容，以及规范模型，用于捕获装置的至少一部分与集成的装置的一个或多个其它导体之间的电容 电路。 规范层次模型可以应用于集成电路的布局。 布局的电容可以基于规范层次模型来确定。

    Method to identify geometrically non-overlapping optimization partitions for parallel timing closure
    2.
    发明申请
    Method to identify geometrically non-overlapping optimization partitions for parallel timing closure 有权
    识别用于并行计时闭合的几何非重叠优化分区的方法

    公开(公告)号：US20050108665A1

    公开(公告)日：2005-05-19

    申请号：US10716772

    申请日：2003-11-19

    申请人： Jose Luis Neves ,  Jiyoun Kim

    发明人： Jose Luis Neves ,  Jiyoun Kim

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/505

    摘要： A method is provided to speed up timing optimization after placement by parallelizing the optimization step. The method includes performing multiple partitions in the set of timing critical paths such that each partition can be optimized independently in a separate processor. To eliminate the need for inter-processor communication, conditions of timing independence and physical independence are imposed on each partition, thereby defining sub-sets of endpoints and paths associated therewith. The optimizing is performed in parallel by the processors, each of the processors optimizing timing of the paths associated with the endpoints in respective sub-sets. In a preferred embodiment, an endpoint graph is constructed from the list of critical paths, where the endpoint graph has at least one vertex representing critical paths associated with a given endpoint. The partitioning step then includes the step of partitioning the endpoint graph to define sub-sets of vertices.

    摘要翻译： 提供了一种通过并行优化步骤来加速放置后的定时优化的方法。 该方法包括在所述一组定时关键路径中执行多个分区，使得可以在单独的处理器中独立地优化每个分区。 为了消除对处理器间通信的需要，对每个分区施加时序独立性和物理独立性的条件，从而定义与其相关联的端点和路径的子集。 优化由处理器并行执行，每个处理器优化与相应子集中的端点相关联的路径的定时。 在优选实施例中，从关键路径列表构建端点图，其中端点图具有表示与给定端点相关联的关键路径的至少一个顶点。 然后，分割步骤包括分割端点图以定义顶点的子集的步骤。

    Method to identify geometrically non-overlapping optimization partitions for parallel timing closure
    5.
    发明授权
    Method to identify geometrically non-overlapping optimization partitions for parallel timing closure 有权
    识别用于并行计时闭合的几何非重叠优化分区的方法

    公开(公告)号：US07047506B2

    公开(公告)日：2006-05-16

    申请号：US10716772

    申请日：2003-11-19

    申请人： Jose Luis Pontes Corrcia Neves ,  Jiyoun Kim

    发明人： Jose Luis Pontes Corrcia Neves ,  Jiyoun Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： A method is provided to speed up timing optimization after placement by parallelizing the optimization step. The method includes performing multiple partitions in the set of timing critical paths such that each partition can be optimized independently in a separate processor. To eliminate the need for inter-processor communication, conditions of timing independence and physical independence are imposed on each partition, thereby defining sub-sets of endpoints and paths associated therewith. The optimizing is performed in parallel by the processors, each of the processors optimizing timing of the paths associated with the endpoints in respective sub-sets. In a preferred embodiment, an endpoint graph is constructed from the list of critical paths, where the endpoint graph has at least one vertex representing critical paths associated with a given endpoint. The partitioning step then includes the step of partitioning the endpoint graph to define sub-sets of vertices.

    摘要翻译： 提供了一种通过并行优化步骤来加速放置后的定时优化的方法。 该方法包括在所述一组定时关键路径中执行多个分区，使得可以在单独的处理器中独立地优化每个分区。 为了消除对处理器间通信的需要，对每个分区施加时序独立性和物理独立性的条件，从而定义与其相关联的端点和路径的子集。 优化由处理器并行执行，每个处理器优化与相应子集中的端点相关联的路径的定时。 在优选实施例中，从关键路径列表构建端点图，其中端点图具有表示与给定端点相关联的关键路径的至少一个顶点。 然后，分割步骤包括分割端点图以定义顶点的子集的步骤。

    Capacitance extraction for advanced device technologies
    6.
    发明授权
    Capacitance extraction for advanced device technologies 有权
    高级器件技术的电容提取

    公开(公告)号：US08522181B2

    公开(公告)日：2013-08-27

    申请号：US13357544

    申请日：2012-01-24

    申请人： Arthur Nieuwoudt ,  Jiyoun Kim ,  Mathew Koshy ,  Baribrata Biswas

    发明人： Arthur Nieuwoudt ,  Jiyoun Kim ,  Mathew Koshy ,  Baribrata Biswas

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5036

    摘要： A technology specific information to design the integrated circuit is received. A plurality of canonical hierarchical models to capture an integrated circuit capacitance are created. The plurality of canonical hierarchical models includes at least a canonical model to capture a capacitance of a device having a plurality of conductors, and a canonical model to capture a capacitance between at least a portion of the device and one or more other conductors of the integrated circuit. The canonical hierarchical models can be applied to a layout of the integrated circuit. A capacitance for the layout can be determined based on the canonical hierarchical models.

    摘要翻译： 接收到设计集成电路的技术特定信息。 创建了用于捕获集成电路电容的多个规范层次模型。 多个规范层级模型至少包括一个规范模型，用于捕获具有多个导体的装置的电容，以及规范模型，用于捕获装置的至少一部分与集成的装置的一个或多个其它导体之间的电容 电路。 规范层次模型可以应用于集成电路的布局。 布局的电容可以基于规范层次模型来确定。