公开(公告)号：US20070145492A1

公开(公告)日：2007-06-28

申请号：US11608635

申请日：2006-12-08

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76855 ,  H01L21/76858 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device includes forming an insulating layer over the semiconductor substrate and the gate electrode. An insulating layer may have a via hole connected to the semiconductor substrate or the gate electrode and a trench connected to the via hole. A first barrier layer and a second barrier layer may be formed. The first barrier layer and the second barrier layer may be annealed to form a silicide and combine the first barrier layer and the second barrier layer to form a metal compound.

摘要翻译： 制造半导体器件的方法包括在半导体衬底和栅电极上形成绝缘层。 绝缘层可以具有连接到半导体衬底或栅电极的通孔以及连接到通孔的沟槽。 可以形成第一阻挡层和第二阻挡层。 第一阻挡层和第二阻挡层可以退火以形成硅化物，并且组合第一阻挡层和第二阻挡层以形成金属化合物。

公开(公告)号：US20070145517A1

公开(公告)日：2007-06-28

申请号：US11611664

申请日：2006-12-15

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L21/76808 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device includes forming an insulation film over a semiconductor substrate having a conduction layer; forming a trench pattern over the insulation film; etching an upper portion of the insulation film by using the trench pattern as a mask to form a trench; removing the trench pattern; forming a spacer film over the insulation film having the trench; etching the space film to form a spacer by using a blanket etching process, the spacer remaining over an edge of an inner portion of the trench; etching the insulation film to form a via hole by using as a mask the spacer; completely removing the spacer; forming a barrier film over sidewalls of the trench and the via hole; and forming a metal line with which fills inner portions of the trench and the via hole.

摘要翻译： 一种制造半导体器件的方法包括在具有导电层的半导体衬底上形成绝缘膜; 在绝缘膜上形成沟槽图案; 通过使用沟槽图案作为掩模蚀刻绝缘膜的上部以形成沟槽; 去除沟槽图案; 在具有沟槽的绝缘膜上形成间隔膜; 通过使用覆盖蚀刻工艺蚀刻空间膜以形成间隔物，间隔物保留在沟槽的内部的边缘上; 通过使用间隔物作为掩模蚀刻绝缘膜以形成通孔; 完全去除垫片; 在沟槽和通孔的侧壁上形成阻挡膜; 并且形成填充沟槽和通孔的内部的金属线。

公开(公告)号：US08039387B2

公开(公告)日：2011-10-18

申请号：US12326905

申请日：2008-12-03

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method for manufacturing the same includes forming a via pattern having a matrix form in a dielectric layer. The via pattern includes a via slit provided at the center of the via pattern and a plurality of via holes provided at an outer periphery of the via pattern and surrounding the via slit. Metal plugs are formed in the via holes.

摘要翻译： 半导体器件及其制造方法包括在电介质层中形成具有矩阵形式的通孔图案。 通孔图案包括设置在通孔图案的中心处的通孔狭缝和设置在通孔图案的外周并围绕通孔狭缝的多个通孔。 金属塞形成在通孔中。

公开(公告)号：US07572694B2

公开(公告)日：2009-08-11

申请号：US11611664

申请日：2006-12-15

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H01L21/8238

CPC分类号： H01L21/76808 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device includes forming an insulation film over a semiconductor substrate having a conduction layer; forming a trench pattern over the insulation film; etching an upper portion of the insulation film by using the trench pattern as a mask to form a trench; removing the trench pattern; forming a spacer film over the insulation film having the trench; etching the space film to form a spacer by using a blanket etching process, the spacer remaining over an edge of an inner portion of the trench; etching the insulation film to form a via hole by using as a mask the spacer; completely removing the spacer; forming a barrier film over sidewalls of the trench and the via hole; and forming a metal line with which fills inner portions of the trench and the via hole.

摘要翻译： 一种制造半导体器件的方法包括在具有导电层的半导体衬底上形成绝缘膜; 在绝缘膜上形成沟槽图案; 通过使用沟槽图案作为掩模蚀刻绝缘膜的上部以形成沟槽; 去除沟槽图案; 在具有沟槽的绝缘膜上形成间隔膜; 通过使用覆盖蚀刻工艺蚀刻空间膜以形成间隔物，间隔物保留在沟槽的内部的边缘上; 通过使用间隔物作为掩模蚀刻绝缘膜以形成通孔; 完全去除垫片; 在沟槽和通孔的侧壁上形成阻挡膜; 并且形成填充沟槽和通孔的内部的金属线。

公开(公告)号：US20090141159A1

公开(公告)日：2009-06-04

申请号：US12326902

申请日：2008-12-03

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H04N5/335

CPC分类号： H04N5/217 ,  H01L27/14603 ,  H01L27/14605 ,  H01L27/14689

摘要： An image sensor and a manufacturing method for an image sensor. An image may include a central pixel array that contains pixels disposed in a center of a pixel area, and a peripheral pixel array that contains pixels disposed in a periphery of the pixel area. A gate oxide layer at a center area of a photodiode may have a smaller thickness than a gate oxide layer of pixels at a center area of the photodiode.

摘要翻译： 图像传感器和图像传感器的制造方法。 图像可以包括包含设置在像素区域的中心的像素的中心像素阵列，以及包含设置在像素区域的周边中的像素的外围像素阵列。 在光电二极管的中心区域的栅氧化层可以具有比光电二极管的中心区域处的像素的栅氧化层更薄的厚度。

公开(公告)号：US20060138587A1

公开(公告)日：2006-06-29

申请号：US11319535

申请日：2005-12-29

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H01L29/00

CPC分类号： H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： An semiconductor device and a manufacturing method minimizes the inductor area in a high frequency device by forming an inductor with a vertical spiral geometry. Accordingly, the device can be highly integrated. In addition, the inductor area overlapped with various devices on a substrate can be minimized so as to prevent deterioration of the electrical characteristics of the inductor.

摘要翻译： 半导体器件和制造方法通过形成具有垂直螺旋几何形状的电感器来最小化高频器件中的电感器面积。 因此，该装置可以高度集成。 此外，与基板上的各种器件重叠的电感器面积可以最小化，以防止电感器的电特性的劣化。

公开(公告)号：US08325262B2

公开(公告)日：2012-12-04

申请号：US12326902

申请日：2008-12-03

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H04N3/14 ,  H04N5/335

CPC分类号： H04N5/217 ,  H01L27/14603 ,  H01L27/14605 ,  H01L27/14689

摘要： An image sensor and a manufacturing method for an image sensor. An image may include a central pixel array that contains pixels disposed in a center of a pixel area, and a peripheral pixel array that contains pixels disposed in a periphery of the pixel area. A gate oxide layer at a center area of a photodiode may have a smaller thickness than a gate oxide layer of pixels at a center area of the photodiode.

摘要翻译： 图像传感器和图像传感器的制造方法。 图像可以包括包含设置在像素区域的中心的像素的中心像素阵列，以及包含设置在像素区域的周边中的像素的外围像素阵列。 在光电二极管的中心区域的栅氧化层可以具有比光电二极管的中心区域处的像素的栅氧化层更薄的厚度。

公开(公告)号：US20090267237A1

公开(公告)日：2009-10-29

申请号：US12497856

申请日：2009-07-06

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H01L23/48

CPC分类号： H01L21/76808 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device includes forming an insulation film over a semiconductor substrate having a conduction layer; forming a trench pattern over the insulation film; etching an upper portion of the insulation film by using the trench pattern as a mask to form a trench; removing the trench pattern; forming a spacer film over the insulation film having the trench; etching the space film to form a spacer by using a blanket etching process, the spacer remaining over an edge of an inner portion of the trench; etching the insulation film to form a via hole by using as a mask the spacer; completely removing the spacer; forming a barrier film over sidewalls of the trench and the via hole; and forming a metal line with which fills inner portions of the trench and the via hole.

摘要翻译： 一种制造半导体器件的方法包括在具有导电层的半导体衬底上形成绝缘膜; 在绝缘膜上形成沟槽图案; 通过使用沟槽图案作为掩模蚀刻绝缘膜的上部以形成沟槽; 去除沟槽图案; 在具有沟槽的绝缘膜上形成间隔膜; 通过使用覆盖蚀刻工艺蚀刻空间膜以形成间隔物，间隔物保留在沟槽的内部的边缘上; 通过使用间隔物作为掩模蚀刻绝缘膜以形成通孔; 完全去除垫片; 在所述沟槽和所述通孔的侧壁上形成阻挡膜; 并且形成填充沟槽和通孔的内部的金属线。

公开(公告)号：US20090140303A1

公开(公告)日：2009-06-04

申请号：US12326905

申请日：2008-12-03

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H01L23/535 ,  H01L21/4763 ,  H01L21/443

CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method for manufacturing the same includes forming a via pattern having a matrix form in a dielectric layer. The via pattern includes a via slit provided at the center of the via pattern and a plurality of via holes provided at an outer periphery of the via pattern and surrounding the via slit. Metal plugs are formed in the via holes.

摘要翻译： 半导体器件及其制造方法包括在电介质层中形成具有矩阵形式的通孔图案。 通孔图案包括设置在通孔图案的中心处的通孔狭缝和设置在通孔图案的外周并围绕通孔狭缝的多个通孔。 金属塞形成在通孔中。

公开(公告)号：US20060160325A1

公开(公告)日：2006-07-20

申请号：US11312387

申请日：2005-12-21

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H01L21/76

CPC分类号： H01L21/31053 ,  H01L21/76229 ,  H01L21/76232

摘要： An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming an insulation layer on a silicon substrate; forming a shallow trench isolation (STI) pattern by a photolithography and etching process; forming a high density plasma (HDP) oxide layer on the STI pattern; forming a barrier layer on the HDP oxide layer; patterning the barrier layer by a photolithography and etching process; and planarizing the HDP oxide layer by CMP. The adoption of the barrier layer can prevent the occurrence of dishing, so pattern failures due to dishing can be suppressed.

摘要翻译： 根据本发明的实施例的制造半导体器件的示例性方法包括在硅衬底上形成绝缘层; 通过光刻和蚀刻工艺形成浅沟槽隔离（STI）图案; 在STI图案上形成高密度等离子体（HDP）氧化物层; 在HDP氧化物层上形成阻挡层; 通过光刻和蚀刻工艺图案化阻挡层; 并通过CMP平坦化HDP氧化物层。 采用阻挡层可以防止凹陷的发生，从而可以抑制由于凹陷引起的图案故障。