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公开(公告)号：US5784700A
公开(公告)日：1998-07-21
申请号：US641820
申请日：1996-05-02
CPC分类号： G06F13/4018 , G06F12/0215 , G06F12/0623
摘要： A memory interface unit capable of coupling a microprocessor to memory external to the microprocessor, wherein the memory can be of at least two types differing in width, and where the data stored in such memory can be in different sizes, and wherein the memory can be formed in sections. The invention utilizes means for controlling at least two strobe signal lines and means for shifting the memory address lines, programmably, so as to accommodate the various combinations of memory width and data size.
摘要翻译： 一种能够将微处理器耦合到微处理器外部的存储器的存储器接口单元，其中存储器可以是宽度不同的至少两种类型，并且其中存储在这种存储器中的数据可以具有不同的尺寸，并且其中存储器可以是 形成在部分。 本发明利用了用于控制至少两个选通信号线的装置以及可编程地移位存储器地址线的装置，以便适应存储器宽度和数据大小的各种组合。
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公开(公告)号：US5761478A
公开(公告)日：1998-06-02
申请号：US653220
申请日：1996-05-24
CPC分类号： G06F13/4018 , G06F12/0215 , G06F12/0623
摘要： A memory interface unit for coupling a microprocessor to a memory external to the microprocessor, the memory being utilized for the storage of data therein and the retrieval of data therefrom, and the memory being provided in one or more memory banks, each of the banks being provided with a set of address lines and a byte enable line, data being transferring to and from each of the memory banks on a group of data lines, and the memory banks being provided in one or more banks whereby the group or groups of data lines, as the case may be, provide a memory data path having a physical transfer width for transfer of data to and from the memory, and the data being stored and retrieved over the memory data path in two or more data types, each type having a different size, the memory interface unit being provided with a set of address pins and a set of strobe pins, comprising. The unit includes a first element for providing an indication of a physical transfer width of a memory coupled to the memory interface unit. Also provided is a second element for providing an indication of a data type to be transferred to or from the memory. A third element, responsive to the first element and the second element, depending on the data type indication, provides to the address pins an address, shifted in position, with at least some of the address lines being for coupling to the address lines of the one or more banks of memory, as the case may be, and with one or more of the address pins being for activation of the byte enable line or lines, as the case may be, for data to be transferred, or, alternatively, providing to the address pins an address, unshifted in position, for coupling to the address lines of the one or more banks of memory, as the case may be, for addressing data to be transferred. Depending on the physical transfer width indication, the third element also causes one or more of the strobe pins to be used as additional address pins.
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