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公开(公告)号：US06522985B1
公开(公告)日：2003-02-18
申请号：US08920643
申请日：1997-08-29
IPC分类号： G06F1126
CPC分类号： G06F11/3656 , G06F8/41 , G06F11/006 , G06F11/2289 , G06F11/261 , G06F11/32 , G06F11/34
摘要： An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control of logical circuitry associated with said emulation device.
摘要翻译： 包括具有至少第一和第二扫描路径的串行扫描可测性接口的仿真设备，以及连接并响应于所述第二扫描路径的状态机电路，其通常可操作用于与所述仿真设备相关联的逻辑电路的仿真控制。
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公开(公告)号：US06704895B1
公开(公告)日：2004-03-09
申请号：US09431802
申请日：1999-11-01
IPC分类号： G01R3128
CPC分类号： G06F11/3664 , G01R31/318505 , G01R31/318536 , G01R31/318558 , G06F11/261 , G06F11/27 , G06F11/2733 , G06F11/36 , G06F11/3636 , G06F11/3648
摘要： An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control.
摘要翻译： 包括具有至少第一和第二扫描路径的串行扫描可测性接口的仿真设备，以及连接并响应于所述第二扫描路径的状态机电路，其通常可操作用于仿真控制。
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公开(公告)号：US5329471A
公开(公告)日：1994-07-12
申请号：US84787
申请日：1993-06-29
IPC分类号： G01R31/3185 , G06F9/45 , G06F11/00 , G06F11/22 , G06F11/26 , G06F11/32 , G06F11/34 , G06F11/36 , G06F15/20
CPC分类号： G06F11/3648 , G01R31/318536 , G01R31/318558 , G06F11/2289 , G06F11/261 , G06F8/41 , G01R31/318505 , G06F11/006 , G06F11/32 , G06F11/34 , G06F11/36
摘要： An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control of logical circuitry associated with said emulation device.
摘要翻译： 包括具有至少第一和第二扫描路径的串行扫描可测性接口的仿真设备，以及连接并响应于所述第二扫描路径的状态机电路，其通常可操作用于与所述仿真设备相关联的逻辑电路的仿真控制。
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公开(公告)号：US06920416B1
公开(公告)日：2005-07-19
申请号：US08720586
申请日：1996-10-02
申请人： Gary L. Swoboda , Henry R. Hoar , Joseph A. Coomes
发明人： Gary L. Swoboda , Henry R. Hoar , Joseph A. Coomes
CPC分类号： G06F11/261 , G06F11/3656
摘要： An electronic system includes electronic circuitry to be tested having serial scan shift register latches, and a serial scan generator embedded in the electronic system upon manufacture and connected to the serial scan shift register latches of the electronic circuitry to facilitate testing. The electronic system may consist of a single printed circuit board mounting both the electronic circuitry and the serial scan generator. The electronic system may consist of a single semiconductor chip carrier mounting both the electronic circuitry and the serial scan generator, are both mounted on said single semiconductor chip carrier. The electronic system may further include a detachable second serial scan generator. The serial scan generator preferably operates slower than the detachable second serial scan generator. The electronic system may further include a disabling terminal disabling the serial scan generator upon attachment of the detachable second serial scan generator.
摘要翻译： 电子系统包括要测试的电子电路，具有串行扫描移位寄存器锁存器，以及串行扫描发生器，其在制造时嵌入电子系统中，并连接到电子电路的串行扫描移位寄存器锁存器以便于测试。 电子系统可以由安装电子电路和串行扫描发生器的单个印刷电路板组成。 电子系统可以由安装电子电路和串行扫描发生器的单个半导体芯片载体组成，均安装在所述单个半导体芯片载体上。 电子系统还可以包括可拆卸的第二串行扫描发生器。 串行扫描发生器优选地比可拆卸的第二串行扫描发生器操作更慢。 电子系统还可以包括禁用终端，在连接可拆卸的第二串行扫描发生器时禁用串行扫描发生器。
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公开(公告)号：US06499122B1
公开(公告)日：2002-12-24
申请号：US09265652
申请日：1999-03-10
申请人： Joseph A. Coomes
发明人： Joseph A. Coomes
IPC分类号： G01R3128
CPC分类号： G01R31/31905
摘要： An apparatus for emulating, testing, interrogating, debugging, and programming an integrated circuit is provided. The apparatus has a boundary scan adapter in association with a host computer for accepting a control signal from the host computer, and for generating an intermediate signal for acceptance by the integrated circuit which intermediate signal is compliant with the specifications of the integrated circuit. Also, the apparatus has an interface associated with the integrated circuit for accepting the intermediate signal from the boundary scan adapter. The control signal from the host computer has a magnitude greater than the magnitude of the intermediate signal which intermediate signal is specific to and compliant with the operation of the integrated circuit.
摘要翻译： 提供了一种用于仿真，测试，询问，调试和编程集成电路的设备。 该装置具有与主计算机相关联的边界扫描适配器，用于接收来自主计算机的控制信号，并且用于产生用于集成电路接受的中间信号，该中间信号符合集成电路的规格。 此外，该装置具有与集成电路相关联的接口，用于接受来自边界扫描适配器的中间信号。 来自主计算机的控制信号的幅度大于中间信号的幅度，其中间信号是专用于并符合集成电路的操作。
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公开(公告)号：US5784700A
公开(公告)日：1998-07-21
申请号：US641820
申请日：1996-05-02
CPC分类号： G06F13/4018 , G06F12/0215 , G06F12/0623
摘要： A memory interface unit capable of coupling a microprocessor to memory external to the microprocessor, wherein the memory can be of at least two types differing in width, and where the data stored in such memory can be in different sizes, and wherein the memory can be formed in sections. The invention utilizes means for controlling at least two strobe signal lines and means for shifting the memory address lines, programmably, so as to accommodate the various combinations of memory width and data size.
摘要翻译： 一种能够将微处理器耦合到微处理器外部的存储器的存储器接口单元，其中存储器可以是宽度不同的至少两种类型，并且其中存储在这种存储器中的数据可以具有不同的尺寸，并且其中存储器可以是 形成在部分。 本发明利用了用于控制至少两个选通信号线的装置以及可编程地移位存储器地址线的装置，以便适应存储器宽度和数据大小的各种组合。
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7.发明授权Electronic systems and emulation and testing devices, cables, systems and methods 失效电子系统和仿真和测试设备，电缆，系统和方法
公开(公告)号：US5684721A
公开(公告)日：1997-11-04
申请号：US851232
申请日：1992-03-13
申请人： Gary L. Swoboda , Henry R. Hoar , Joseph A. Coomes
发明人： Gary L. Swoboda , Henry R. Hoar , Joseph A. Coomes
IPC分类号： G01R31/3185 , G06F11/26 , G06F11/36 , G06F17/00 , G06G7/06
CPC分类号： G06F11/3656 , G01R31/318536 , G06F11/261
摘要： An electronic system for use with a host computer. The system includes electronic circuitry including a first semiconductor chip generally operable for a first function and also adapted for input and output of emulation signals. This is combined with emulation circuitry including a second semiconductor chip adapted for connection to the host computer. The emulation circuitry is connected to the electronic circuitry to generate emulation signals to input to the electronic circuitry and to accept emulation signals from the electronic circuitry. A physical assembly supports the emulation circuitry and the electronic circuitry as a unit. Other electronic systems and emulation and testing devices, cables, systems and methods are also disclosed.
摘要翻译： 一种用于主计算机的电子系统。 该系统包括电子电路，其包括通常可用于第一功能并且还适于输入和输出仿真信号的第一半导体芯片。 这与仿真电路组合，包括适于连接到主计算机的第二半导体芯片。 仿真电路连接到电子电路以产生仿真信号以输入到电子电路并接收来自电子电路的仿真信号。 物理组件支持仿真电路和电子电路作为一个单元。 还公开了其它电子系统和仿真和测试装置，电缆，系统和方法。
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公开(公告)号：US5761478A
公开(公告)日：1998-06-02
申请号：US653220
申请日：1996-05-24
CPC分类号： G06F13/4018 , G06F12/0215 , G06F12/0623
摘要： A memory interface unit for coupling a microprocessor to a memory external to the microprocessor, the memory being utilized for the storage of data therein and the retrieval of data therefrom, and the memory being provided in one or more memory banks, each of the banks being provided with a set of address lines and a byte enable line, data being transferring to and from each of the memory banks on a group of data lines, and the memory banks being provided in one or more banks whereby the group or groups of data lines, as the case may be, provide a memory data path having a physical transfer width for transfer of data to and from the memory, and the data being stored and retrieved over the memory data path in two or more data types, each type having a different size, the memory interface unit being provided with a set of address pins and a set of strobe pins, comprising. The unit includes a first element for providing an indication of a physical transfer width of a memory coupled to the memory interface unit. Also provided is a second element for providing an indication of a data type to be transferred to or from the memory. A third element, responsive to the first element and the second element, depending on the data type indication, provides to the address pins an address, shifted in position, with at least some of the address lines being for coupling to the address lines of the one or more banks of memory, as the case may be, and with one or more of the address pins being for activation of the byte enable line or lines, as the case may be, for data to be transferred, or, alternatively, providing to the address pins an address, unshifted in position, for coupling to the address lines of the one or more banks of memory, as the case may be, for addressing data to be transferred. Depending on the physical transfer width indication, the third element also causes one or more of the strobe pins to be used as additional address pins.
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公开(公告)号：US5594914A
公开(公告)日：1997-01-14
申请号：US326677
申请日：1994-10-20
CPC分类号： G06F9/30043 , G06F9/34 , G06F9/3842 , G06F9/3861
摘要： A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address. Further included is an arithmetic logic unit operative to perform an arithmetic operation on data received by the arithmetic unit and to combine the contents of the program register with a data field decoded from the block instruction by the instruction decode and control unit to generate a block end address, and a block handler unit, having a block start register operative to store the contents of the program register, is responsive to the control signals from the instruction decode and control unit to store the program address corresponding to the block start address to the block start register wherein the contents of the block start register correspond to a start address for a block of instructions to be executed. Other devices, systems and methods are also disclosed.
摘要翻译： 一种数据处理装置，包括用于产生建立指令周期的脉冲的时钟发生器，通过断言地址可访问的存储器，指令解码和控制单元，具有可操作以保存程序指令的指令寄存器，用于解码提供控制信号的程序指令 根据管理组织来控制每个指令周期内的数据处理设备的操作，并且响应于表示块指令的指令代码启动块序列。 具有用于保存与程序地址相对应的程序计数的程序寄存器的程序定序器电路可操作以利用程序寄存器的内容访问存储器，以获得与程序地址相对应的程序指令。 进一步包括的算术逻辑单元可操作以对由算术单元接收的数据进行算术运算，并将程序寄存器的内容与由指令解码和控制单元从块指令解码的数据字段组合，以生成块结束 地址和块处理器单元，具有用于存储程序寄存器的内容的块起始寄存器，响应于来自指令解码和控制单元的控制信号，将对应于块起始地址的程序地址存储到块 起始寄存器，其中块起始寄存器的内容对应于要执行的指令块的起始地址。 还公开了其他装置，系统和方法。
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公开(公告)号：US5535348A
公开(公告)日：1996-07-09
申请号：US420932
申请日：1995-04-12
CPC分类号： G06F9/30043 , G06F9/34 , G06F9/3842 , G06F9/3861
摘要： A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address. Further included is an arithmetic logic unit operative to perform an arithmetic operation on data received by the arithmetic unit and to combine the contents of the program register with a data field decoded from the block instruction by the instruction decode and control unit to generate a block end address, and a block handler unit, having a block start register operative to store the contents of the program register, is responsive to the control signals from the instruction decode and control unit to store the program address corresponding to the block start address to the block start register wherein the contents of the block start register correspond to a start address for a block of instructions to be executed. Other devices, systems and methods are also disclosed.
摘要翻译： 一种数据处理装置，包括用于产生建立指令周期的脉冲的时钟发生器，通过断言地址可访问的存储器，指令解码和控制单元，具有可操作以保存程序指令的指令寄存器，用于解码提供控制信号的程序指令 根据管理组织来控制每个指令周期内的数据处理设备的操作，并且响应于表示块指令的指令代码启动块序列。 具有用于保存与程序地址相对应的程序计数的程序寄存器的程序定序器电路可操作以利用程序寄存器的内容访问存储器，以获得与程序地址相对应的程序指令。 进一步包括的算术逻辑单元可操作以对由算术单元接收的数据进行算术运算，并将程序寄存器的内容与由指令解码和控制单元从块指令解码的数据字段组合，以生成块结束 地址和块处理器单元，具有用于存储程序寄存器的内容的块起始寄存器，响应于来自指令解码和控制单元的控制信号，将对应于块起始地址的程序地址存储到块 起始寄存器，其中块起始寄存器的内容对应于要执行的指令块的起始地址。 还公开了其他装置，系统和方法。
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