公开(公告)号：US08713409B1

公开(公告)日：2014-04-29

申请号：US13525922

申请日：2012-06-18

申请人： Chen W. Tseng ,  Weiguang Lu ,  Christopher Y. Karman

发明人： Chen W. Tseng ,  Weiguang Lu ,  Christopher Y. Karman

IPC分类号： G11C29/00

CPC分类号： G11C29/52 ,  G11C5/005 ,  G11C11/4125 ,  G11C2029/0409

摘要： Approaches for mitigating single event upsets (SEUs) in a circuit arrangement. In response to each bit error of a plurality of bit errors, an error address indicative of the bit error in a configuration memory cell in the circuit arrangement is translated into a non-volatile memory address. A partial bitstream at the non-volatile memory address is read from a non-volatile memory. Successive partial bitstreams read in response to successive ones of the bit errors are alternately transmitted to first and second internal configuration ports. A subset of configuration memory cells of the circuit arrangement, including the configuration memory cell referenced by the error address, is reconfigured with the partial bitstream.

摘要翻译： 减轻电路安排中的单事件扰乱（SEU）的方法。 响应于多个比特错误的每个比特错误，指示电路布置中的配置存储单元中的比特错误的错误地址被转换为非易失性存储器地址。 从非易失性存储器读取非易失性存储器地址处的部分比特流。 响应于连续的位错误而读取的连续的部分比特流被交替地发送到第一和第二内部配置端口。 包括由错误地址引用的配置存储器单元的电路装置的配置存储器单元的子集与部分位流重新配置。