公开(公告)号：US07228468B2

公开(公告)日：2007-06-05

申请号：US11001345

申请日：2004-11-30

申请人： Cheng-Wen Wu ,  Rei-Fu Huang ,  Chin-Lung Su ,  Wen-Ching Wu ,  Yeong-Jar Chang ,  Kun-Lun Luo ,  Shen-Tien Lin

发明人： Cheng-Wen Wu ,  Rei-Fu Huang ,  Chin-Lung Su ,  Wen-Ching Wu ,  Yeong-Jar Chang ,  Kun-Lun Luo ,  Shen-Tien Lin

IPC分类号： G11C29/00

CPC分类号： G11C29/4401 ,  G11C29/16 ,  G11C29/44 ,  G11C29/72 ,  G11C2029/0405 ,  G11C2029/3602

摘要： The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.

摘要翻译： 本发明提供一种存储器建立自诊断和修复的方法和装置，其具有综合征识别。 它在测试过程中使用故障模式识别和故障排序格式结构来识别存储器中的故障行，故障列和单个故障字，然后输出故障信息。 基于综合信息，应用冗余分析算法来分配修复故障存储单元的备用存储单元。 它具有具有增强的故障综合征识别的定序器，具有改进的冗余利用率的内置冗余分析电路，以及在正常访问期间减少定时损失的地址可重新配置电路。 本发明减少了自动测试设备中的占用时间和所需的捕获存储空间。 它还增加了修复率，并减少了所需的面积开销。

公开(公告)号：US20060064618A1

公开(公告)日：2006-03-23

申请号：US11001345

申请日：2004-11-30

申请人： Cheng-Wen Wu ,  Rei-Fu Huang ,  Chin-Lung Su ,  Wen-Ching Wu ,  Yeong-Jar Chang ,  Kun-Lun Luo ,  Shen-Tien Lin

发明人： Cheng-Wen Wu ,  Rei-Fu Huang ,  Chin-Lung Su ,  Wen-Ching Wu ,  Yeong-Jar Chang ,  Kun-Lun Luo ,  Shen-Tien Lin

IPC分类号： G01R31/28

CPC分类号： G11C29/4401 ,  G11C29/16 ,  G11C29/44 ,  G11C29/72 ,  G11C2029/0405 ,  G11C2029/3602

摘要： The present invention provides a method and apparatus for a memory build-in self-diagnosis and repair with syndrome identification. It uses a fail-pattern identification and a syndrome-format structure to identify faulty rows, faulty columns and single faulty word in the memory during the testing process, then exports the syndrome information. Based on the syndrome information, a redundancy analysis algorithm is applied to allocate the spare memory elements repairing the faulty memory cells. It has a sequencer with enhanced fault syndrome identification, a build-in redundancy-analysis circuit with improved redundancy utilization, and an address reconfigurable circuit with reduced timing penalty during normal access. The invention reduces the occupation time and the required capture memory space in the automatic test equipment. It also increases the repair rate and reduces the required area overhead.

摘要翻译： 本发明提供一种存储器建立自诊断和修复的方法和装置，其具有综合征识别。 它在测试过程中使用故障模式识别和故障排序格式结构来识别存储器中的故障行，故障列和单个故障字，然后输出故障信息。 基于综合信息，应用冗余分析算法来分配修复故障存储单元的备用存储单元。 它具有具有增强的故障综合征识别的定序器，具有改进的冗余利用率的内置冗余分析电路，以及在正常访问期间减少定时损失的地址可重构电路。 本发明减少了自动测试设备中的占用时间和所需的捕获存储空间。 它还增加了修复率，并减少了所需的面积开销。

公开(公告)号：US20070288807A1

公开(公告)日：2007-12-13

申请号：US11742567

申请日：2007-04-30

申请人： Cheng-Wen Wu ,  Rei-Fu Huang ,  Chin-Lung Su ,  Wen-Ching Wu ,  Kun-Lun Luo

发明人： Cheng-Wen Wu ,  Rei-Fu Huang ,  Chin-Lung Su ,  Wen-Ching Wu ,  Kun-Lun Luo

IPC分类号： G11C29/12

CPC分类号： G11C29/44 ,  G11C29/4401 ,  G11C29/72

摘要： Disclosed is a build-in self-diagnosis and repair method and apparatus in a memory with syndrome identification. It applies a fail-pattern identification and a syndrome-format structure to identify at least one type of faulty syndrome in the memory during a memory testing, then generates and exports fault syndrome information associated with the corresponding faulty syndrome. According to the fault syndrome information, the method applies a redundancy analysis algorithm, allocates spare memory elements and repairs the faulty cells in the memory. The syndrome-format structure respectively applies single-faulty-word-syndrome format, faulty-row-segment-syndrome format, and faulty-column-segment-syndrome format for different faulty syndromes, such as faulty row segments and single faulty words, faulty column segments and single faulty words, all of single faulty words, faulty row segments and faulty column segments, and so on.

摘要翻译： 公开了一种在具有综合征识别的记忆中的内置自诊断和修复方法和装置。 它在存储器测试期间应用故障模式识别和综合征格式结构来识别存储器中的至少一种类型的故障综合征，然后产生并输出与相应的故障综合征相关的故障综合征信息。 根据故障综合信息，该方法应用冗余分析算法，分配备用存储器元件并修复存储器中的故障单元。 综合征格式结构分别针对不良故障综合征，如有缺陷的行段和单一故障字，分别应用单故障字综合征格式，故障行段综合征格式和故障列段综合征格式， 列段和单个故障单词，所有单个故障字，故障行段和故障列段等。

公开(公告)号：US07644323B2

公开(公告)日：2010-01-05

申请号：US11742567

申请日：2007-04-30

申请人： Cheng-Wen Wu ,  Rei-Fu Huang ,  Chin-Lung Su ,  Wen-Ching Wu ,  Kun-Lun Luo

发明人： Cheng-Wen Wu ,  Rei-Fu Huang ,  Chin-Lung Su ,  Wen-Ching Wu ,  Kun-Lun Luo

IPC分类号： G11C29/00

CPC分类号： G11C29/44 ,  G11C29/4401 ,  G11C29/72

摘要： Disclosed is a build-in self-diagnosis and repair method and apparatus in a memory with syndrome identification. It applies a fail-pattern identification and a syndrome-format structure to identify at least one type of faulty syndrome in the memory during a memory testing, then generates and exports fault syndrome information associated with the corresponding faulty syndrome. According to the fault syndrome information, the method applies a redundancy analysis algorithm, allocates spare memory elements and repairs the faulty cells in the memory. The syndrome-format structure respectively applies single-faulty-word-syndrome format, faulty-row-segment-syndrome format, and faulty-column-segment-syndrome format for different faulty syndromes, such as faulty row segments and single faulty words, faulty column segments and single faulty words, all of single faulty words, faulty row segments and faulty column segments, and so on.

摘要翻译： 公开了一种在具有综合征识别的记忆中的内置自诊断和修复方法和装置。 它在存储器测试期间应用故障模式识别和综合征格式结构来识别存储器中的至少一种类型的故障综合征，然后产生并输出与相应的故障综合征相关的故障综合征信息。 根据故障综合信息，该方法应用冗余分析算法，分配备用存储器元件并修复存储器中的故障单元。 综合征格式结构分别针对不良故障综合征，如有缺陷的行段和单一故障字，分别应用单故障字综合征格式，故障行段综合征格式和故障列段综合征格式， 列段和单个故障单词，所有单个故障字，故障行段和故障列段等。

公开(公告)号：US07319625B2

公开(公告)日：2008-01-15

申请号：US11481966

申请日：2006-07-07

申请人： Yeong-Jar Chang ,  Kun-Lun Luo ,  Jung-Chi Ho ,  Cheng-Wen Wu ,  Chin-Jung Su

发明人： Yeong-Jar Chang ,  Kun-Lun Luo ,  Jung-Chi Ho ,  Cheng-Wen Wu ,  Chin-Jung Su

IPC分类号： G11C7/00

CPC分类号： G11C29/12 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/5006

摘要： A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.

摘要翻译： 公开了一种用于测试芯片上的存储器的内置存储器电流测试电路，其包括内置的自测电路和动态电流产生模块。 内置自检电路设置在芯片上，以接收和处理测试信号，并产生控制信号以控制存储器的操作和电流控制代码。 也设置在芯片上的动态电流产生模块基于当前控制码产生到存储器中的测试电流。 内置存储器电流测试电路中的当前切换时间减少，因此可以执行组合功能和应力测试的集成测试。

公开(公告)号：US20070153597A1

公开(公告)日：2007-07-05

申请号：US11481966

申请日：2006-07-07

申请人： Yeong-Jar Chang ,  Kun-Lun Luo ,  Jung-Chi Ho ,  Cheng-Wen Wu ,  Chin-Jung Su

发明人： Yeong-Jar Chang ,  Kun-Lun Luo ,  Jung-Chi Ho ,  Cheng-Wen Wu ,  Chin-Jung Su

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/12 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/5006

摘要： A built-in memory current test circuit to test a memory on a chip is disclosed, comprising a built-in self-test circuit and a dynamic current generation module. The built-in self-test circuit is disposed on the chip to receive and process a test signal and generate a control signal to control operation of the memory and a current control code. The dynamic current generation module, also disposed on the chip, produces a test current into the memory based on the current control code. The current switch time is reduced in the built-in memory current test circuit, and an integrated test combining functional and stress tests can thus be performed.

摘要翻译： 公开了一种用于测试芯片上的存储器的内置存储器电流测试电路，其包括内置的自测电路和动态电流产生模块。 内置自检电路设置在芯片上，以接收和处理测试信号，并产生控制信号以控制存储器的操作和电流控制代码。 也设置在芯片上的动态电流产生模块基于当前控制码产生到存储器中的测试电流。 内置存储器电流测试电路中的当前切换时间减少，因此可以执行组合功能和应力测试的集成测试。

公开(公告)号：US20060253723A1

公开(公告)日：2006-11-09

申请号：US11197657

申请日：2005-08-04

申请人： Cheng-Wen Wu ,  Chin-Lung Su ,  Yi-Ting Yeh

发明人： Cheng-Wen Wu ,  Chin-Lung Su ,  Yi-Ting Yeh

IPC分类号： G11C7/10 ,  G06F11/00

CPC分类号： G11C29/72 ,  G06F11/1044

摘要： A semiconductor memory employs the redundancy memory technique and the error correction code technique and method of correcting errors. The method of correcting errors reads data bits and a checking bit from a predetermined unit of a first memory array such as a main memory array, and the data bits are checked based on the checking bit to determine if there is any error. If there is an error in the data bits, the checking bit is used to correct the error and the data bits together with the checking bit are written back to the predetermined unit. If there is still error in the data bits after the read-check-write process is repeated a predetermined number of times, the predetermined unit is marked as a faulty unit and the data bits together with the checking bit are written to a second memory array such as a redundancy memory array.

摘要翻译： 半导体存储器采用冗余存储器技术和纠错码技术以及校正错误的方法。 校正错误的方法从诸如主存储器阵列的第一存储器阵列的预定单元读取数据位和检查位，并且基于检查位来检查数据位，以确定是否存在任何错误。 如果数据位存在错误，则使用校验位来校正错误，并将数据位与校验位一起写回预定单元。 如果在读取 - 写入处理重复预定次数之后数据位仍然存在错误，则将预定单元标记为故障单元，并将数据位与检查位一起写入第二存储器阵列 例如冗余存储器阵列。

公开(公告)号：US20100080509A1

公开(公告)日：2010-04-01

申请号：US12419862

申请日：2009-04-07

申请人： Cheng-Wen Wu

发明人： Cheng-Wen Wu

IPC分类号： G02B6/26

CPC分类号： G02B6/2835 ,  G02B6/3594

摘要： A fiber loop formed by bending of a connection section between the first fiber and the second fiber includes a coupling region and an upper taper region as well as a down taper region arranged symmetrically on two sides of the coupling region. Then the fiber optic splitter with the fiber loop is assembled with a splitting ratio modulation mechanism. Thus the manufacturing of the fiber optic power splitter with variable splitting ratio is simplified and this favors production and applications of the device. Moreover, the splitting and modulation quality of the splitter are stable and are controlled precisely. Thus the economic benefits of the device in manufacturing, operation quality and product competitiveness are all improved.

摘要翻译： 通过在第一纤维和第二纤维之间的连接部分的弯曲形成的纤维环包括耦合区域和上锥形区域以及对称地布置在耦合区域的两侧上的向下锥形区域。 然后将具有光纤回路的光纤分路器与分束比调制机构组合。 因此，具有可变分流比的光纤功率分配器的制造被简化，这有利于器件的生产和应用。 此外，分离器的分离和调制质量稳定，精确控制。 因此，设备在制造，经营质量和产品竞争力方面的经济效益都有所改善。

公开(公告)号：US20070232240A1

公开(公告)日：2007-10-04

申请号：US11761964

申请日：2007-06-12

申请人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

发明人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Yu-Tsao Hsing

IPC分类号： H04B1/38

CPC分类号： H04B17/0085 ,  G01R31/3025 ,  G01R31/303

摘要： The present invention discloses a probing system for integrated circuit devices, which transmits testing data between an automatic test equipment (ATE) and an integrated circuit device. The ATE includes a first transceiving module, and the integrated circuit device includes a core circuit, a built-in self-test (BIST) circuit electrically connected to the core circuit, a controller configured to control the operation of the BIST circuit, and a second transceiving module configured to exchange testing data with the first transceiving module. Preferably, the integrated circuit device further includes a clock generator and a power regulator electrically connected to the second transceiving module, wherein the ATE transmits a radio frequency signal via the first transceiving module, and the second transceiving module receives the radio frequency signal to drive the power regulator to generate power for the integrated circuit device to initiate the BIST circuit.

摘要翻译： 本发明公开了一种用于在自动测试设备（ATE）和集成电路设备之间传输测试数据的集成电路设备的探测系统。 ATE包括第一收发模块，集成电路装置包括核心电路，电连接到核心电路的内置自测试（BIST）电路，被配置为控制BIST电路的操作的控制器，以及 第二收发模块被配置为与第一收发模块交换测试数据。 优选地，集成电路装置还包括时钟发生器和电连接到第二收发模块的功率调节器，其中ATE经由第一收发模块发送射频信号，第二收发模块接收射频信号以驱动 电源调节器为集成电路器件产生电源以启动BIST电路。

公开(公告)号：US07117409B2

公开(公告)日：2006-10-03

申请号：US10735298

申请日：2003-12-12

申请人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Chih-Wea Wang ,  Kao-Liang Cheng

发明人： Cheng-Wen Wu ,  Chih-Tsun Huang ,  Chih-Wea Wang ,  Kao-Liang Cheng

IPC分类号： G11C20/10 ,  G11C7/22

CPC分类号： G11C29/025 ,  G11C8/16 ,  G11C29/02 ,  G11C29/50012

摘要： In a method of testing a multi-port memory in accordance with a test pattern, test clock signals having the same test clock frequency but with different delay periods introduced therein are generated for controlling memory access through the different access ports of the memory. Consecutive memory operations of a test element of the test pattern are then conducted in a folded sequence upon a memory cell through the different access ports in accordance with the test clock signals such that the memory operations are completed within the same test clock cycle of the test element.

摘要翻译： 在根据测试模式测试多端口存储器的方法中，生成具有相同测试时钟频率但具有不同延迟周期的测试时钟信号，用于控制通过存储器的不同访问端口的存储器访问。 测试模式的测试元件的连续存储器操作然后按照测试时钟信号通过不同的存取端口以折叠的顺序进行到存储器单元上，使得存储器操作在测试的相同测试时钟周期内完成 元件。