公开(公告)号：US20120032718A1

公开(公告)日：2012-02-09

申请号：US12851209

申请日：2010-08-05

申请人： Chi Fat CHAN ,  Chien-Wei LIN ,  Gordon CHUNG

发明人： Chi Fat CHAN ,  Chien-Wei LIN ,  Gordon CHUNG

IPC分类号： H03L7/08

CPC分类号： H03L7/093 ,  H03L2207/06 ,  H03L2207/50

摘要： A Digital Phase-Locked Loop (DPLL) has a digitally-controlled oscillator (DCO) that generates an output clock frequency determined by a digital input with most-significant-bits (MSB's) and a least-significant-bit (LSB). The LSB is generated by a Pulse-Width-Modulation (PWM) controller clocked by a control clock that is the output clock divided by C. A reference clock is compared to a feedback clock that is the output clock divided by M. The PWM controller generates M/C LSB's for each reference clock period and loads them in parallel to a parallel-to-serial shift register that serially delivers the LSBs. The pulse width is determined by a fine digital loop filter that filters phase comparison results using a fine time resolution. A coarse digital loop filter generates the MSB's from phase comparison results using a coarse time resolution. LSB waveforms are dithered by randomly selecting high-going or low-going pulses and randomly adjusting pulse widths.

摘要翻译： 数字锁相环（DPLL）具有数字控制振荡器（DCO），用于产生由具有最高有效位（MSB）和最低有效位（LSB）的数字输入确定的输出时钟频率。 LSB由由控制时钟控制的脉冲宽度调制（PWM）控制器产生，控制时钟是输出时钟除以C。将参考时钟与输出时钟除以M的反馈时钟进行比较。PWM控制器 为每个参考时钟周期生成M / C LSB，并将它们并行并行串行传输LSB的并行到串行移位寄存器。 脉冲宽度由精细的数字环路滤波器确定，可以使用精细的时间分辨率对相位比较结果进行滤波。 粗略的数字环路滤波器使用粗略的时间分辨率从相位比较结果生成MSB。 通过随机选择高电平或低电平脉冲和随机调整脉冲宽度，对LSB波形进行抖动。