公开(公告)号：US20140223257A1

公开(公告)日：2014-08-07

申请号：US14165820

申请日：2014-01-28

申请人： Chi-Sung OH ,  Chul-Sung PARK ,  Sang-Bo LEE ,  Dong-Hyun SOHN

发明人： Chi-Sung OH ,  Chul-Sung PARK ,  Sang-Bo LEE ,  Dong-Hyun SOHN

IPC分类号： G06F11/10

CPC分类号： G06F11/1048 ,  G06F11/16 ,  G11C11/005 ,  G11C11/40 ,  G11C11/4076 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/785 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/1202 ,  G11C2029/1204

摘要： A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

摘要翻译： 公开了可以使用纠错电路校正错误数据的半导体存储器件。 半导体存储器件可以包括DRAM单元阵列，奇偶校验发生器，非易失性存储单元阵列和纠错电路。 奇偶校验发生器被配置为基于输入数据生成具有至少一个位的第一组奇偶校验位。 非易失性存储单元阵列可以存储对应于输入数据的输入数据和第一组奇偶校验位，并且输出与输入数据相对应的第一数据，以及对应于第一组奇偶校验位的第二组奇偶校验位。 误差校正电路被配置为基于第一数据生成作为校正数据的第二数据。

公开(公告)号：US20090045844A1

公开(公告)日：2009-02-19

申请号：US12191531

申请日：2008-08-14

申请人： Yong-Hwan NOH ,  Chul-Sung PARK

发明人： Yong-Hwan NOH ,  Chul-Sung PARK

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

摘要翻译： 提供了一种电平转换器和具有使用其的片外驱动器（OCD）的半导体器件。 电平移位器包括多个串联连接的逻辑门，其接收具有第一电源电压电平的第一状态输入信号，并产生具有第二电源电压电平的电平移位的第一状态输出信号。 逻辑门作为电源电压接收至少一个中间电源电压，其具有在第一电源电压电平和第二电源电压电平之间的中间的至少一个电压电平，并且施加到本逻辑门的中间电源电压为 等于或高于施加到先前逻辑门的中间电源电压。

公开(公告)号：US20100194433A1

公开(公告)日：2010-08-05

申请号：US12759252

申请日：2010-04-13

申请人： Yong-Hwan NOH ,  Chul-Sung PARK

发明人： Yong-Hwan NOH ,  Chul-Sung PARK

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

摘要翻译： 提供了一种电平转换器和具有使用其的片外驱动器（OCD）的半导体器件。 电平移位器包括多个串联连接的逻辑门，其接收具有第一电源电压电平的第一状态输入信号，并产生具有第二电源电压电平的电平移位的第一状态输出信号。 逻辑门作为电源电压接收至少一个中间电源电压，其具有在第一电源电压电平和第二电源电压电平之间的中间的至少一个电压电平，并且施加到本逻辑门的中间电源电压为 等于或高于施加到先前逻辑门的中间电源电压。

公开(公告)号：US20080165610A1

公开(公告)日：2008-07-10

申请号：US11845191

申请日：2007-08-27

申请人： Young-Seung KIM ,  Chul-Sung PARK

发明人： Young-Seung KIM ,  Chul-Sung PARK

IPC分类号： G11C8/00

CPC分类号： G11C11/413

摘要： A semiconductor memory device capable of synchronous/asynchronous operation and data input/output method thereof are provided. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to write data to a cell in the memory cell array and to read data from the cell, and a bypass control unit configured to control a late write operation and a bypass operation of the peripheral circuit according to mode conversion of the semiconductor memory device. Accordingly, data coherency can be maintained. In addition, dummy cycle time that may occur during the mode conversion can be prevented by generating a mode conversion signal only in response to toggling of a clock signal.

摘要翻译： 提供能够进行同步/异步操作的半导体存储器件及其数据输入/输出方法。 半导体存储器件包括存储单元阵列，外围电路，被配置为向存储单元阵列中的单元写入数据并从单元读取数据;以及旁路控制单元，被配置为控制延迟写入操作和旁路操作 外围电路根据半导体存储器件的模式转换。 因此，可以保持数据一致性。 此外，可以通过仅响应于时钟信号的切换而产生模式转换信号来防止在模式转换期间可能发生的伪周期时间。