公开(公告)号：US12026608B2

公开(公告)日：2024-07-02

申请号：US16710296

申请日：2019-12-11

申请人： DENSO CORPORATION

发明人： Irina Kataeva ,  Shigeki Otsuka

IPC分类号： G06N3/06 ,  G06N3/065 ,  G06N3/08 ,  G06N3/084 ,  G06N5/046 ,  G06N20/00 ,  G11C11/40 ,  G11C11/54

CPC分类号： G06N3/065 ,  G06N3/084 ,  G06N5/046 ,  G06N20/00 ,  G11C11/40 ,  G11C11/54

摘要： A method for adjusting output level of a neuron in a multilayer neural network is provided. The multilayer neural network includes a memristor and an analog processing circuit, causing transmission of the signals between the neurons and the signal processing in the neurons to be performed in an analog region. The method includes an adjustment step that adjusts an output level of the neurons of each of the layers, causing the output value to become lower than a write threshold voltage of the memristor and to fall within a maximum output range set for the analog processing circuit executing the generation of the output value in accordance with the activation function when each of the output values of the neurons of each of the layers becomes highest.

公开(公告)号：US12014767B2

公开(公告)日：2024-06-18

申请号：US18208050

申请日：2023-06-09

申请人： UNIQUIFY, INC.

发明人： Mahesh Gopalan ,  David Wu ,  Venkat Iyer

IPC分类号： G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/12 ,  G06F1/14 ,  G06F3/06 ,  G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/02 ,  G11C7/04 ,  G11C11/40

CPC分类号： G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/12 ,  G06F1/14 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/067 ,  G06F12/0646 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C7/04 ,  G11C11/40

摘要： A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

公开(公告)号：US11967393B2

公开(公告)日：2024-04-23

申请号：US17472542

申请日：2021-09-10

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Jian Luo ,  Zhuqin Duan

IPC分类号： G11C5/14 ,  G06F1/06 ,  G11C11/40

CPC分类号： G11C5/148 ,  G06F1/06 ,  G11C11/40

摘要： A semiconductor device includes a clock gating circuit and a control circuit. The clock gating circuit outputs a gated clock signal based on a clock signal. Transitions of the clock signal are output in the gated clock signal in response to a clock enable signal having an enable value and are disabled from being output in the gated clock signal in response to the clock enable signal having a disable value. The control circuit includes a first portion that operates based on the clock signal. The first portion sets the clock enable signal to the disable value in response to a disable control and sets the clock enable signal to the enable value in response to a wakeup control. The control circuit includes a second portion that operates based on the gated clock signal. The second portion provides the disable control to the first portion during an operation.

公开(公告)号：US20230317125A1

公开(公告)日：2023-10-05

申请号：US18043103

申请日：2021-08-23

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Shunpei YAMAZAKI

IPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C11/40

CPC分类号： G11C7/1096 ,  G11C11/4096 ,  G11C11/40

摘要： A data semiconductor device with a long retention time is provided. The semiconductor device includes a first transistor, a second transistor, a ferroelectric capacitor, a first capacitor, and a memory cell. Note that the memory cell includes a third transistor. A first gate of the first transistor is electrically connected to a first terminal of the ferroelectric capacitor, and a first terminal of the first transistor is electrically connected to a second gate of the first transistor and a first terminal of the second transistor. A second terminal of the second transistor is electrically connected to a second terminal of the ferroelectric capacitor and a first terminal of the first capacitor. A back gate of the third transistor is electrically connected to the first terminal of the first transistor. In the above structure, the threshold voltage of the third transistor can be increased by supplying a negative potential to the first terminal of the first transistor.

公开(公告)号：US20180358365A1

公开(公告)日：2018-12-13

申请号：US15861845

申请日：2018-01-04

申请人： SK hynix Inc.

发明人： Ki Hong LEE

IPC分类号： H01L27/11 ,  H01L23/532 ,  G11C11/40

CPC分类号： H01L27/1104 ,  G11C11/40 ,  G11C16/14 ,  G11C16/26 ,  G11C2216/04 ,  H01L23/53295 ,  H01L27/11582 ,  H01L2224/32148

摘要： A semiconductor device includes a stacked structure, channel layers passing through the stacked structure, a well plate located under the stacked structure, a source layer located between the stacked structure and the well plate, a connection structure coupling the channel layers to each other and including a first contact contacting the source layer and a second contact contacting the well plate, and an isolation pattern insulating the source layer and the well plate from each other.

公开(公告)号：US20180350423A1

公开(公告)日：2018-12-06

申请号：US16001420

申请日：2018-06-06

申请人： International Business Machines Corporation

发明人： KARL R. ERICKSON ,  PHIL C. PAONE ,  GEORGE F. PAULIK ,  DAVID P. PAULSEN ,  JOHN E. SHEETS, II ,  GREGORY J. UHLMANN

IPC分类号： G11C11/24 ,  G11C11/40

CPC分类号： G11C11/24 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/40 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004 ,  G11C29/50008 ,  G11C2029/0403 ,  G11C2029/5004 ,  G11C2207/2254

摘要： Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.

公开(公告)号：US20180246662A1

公开(公告)日：2018-08-30

申请号：US15884693

申请日：2018-01-31

申请人： SK hynix Inc.

发明人： Jung Hyun KIM

IPC分类号： G06F3/06 ,  G06F1/32

CPC分类号： G06F3/0625 ,  G06F1/3275 ,  G06F1/3296 ,  G06F3/0634 ,  G06F3/0679 ,  G11C5/04 ,  G11C5/148 ,  G11C7/04 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4074 ,  Y02D10/14 ,  Y02D10/172

摘要： A memory module may include a memory device and a power controller. The memory device may operate by being supplied with a first memory power supply voltage and a second memory power supply voltage. The power controller may receive a first power supply voltage and a second power supply voltage from a power source, and supply the first memory power supply voltage and the second memory power supply voltage by changing levels of the first power supply voltage and the second power supply voltage based on operation state information.

公开(公告)号：US10020822B2

公开(公告)日：2018-07-10

申请号：US15323598

申请日：2015-07-20

申请人： Rensselaer Polytechnic Institute

发明人： Tong Zhang ,  Hao Wang

IPC分类号： H03M13/15 ,  G06F3/06 ,  G06F11/10 ,  H03M13/00

CPC分类号： H03M13/154 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1076 ,  G11C11/40 ,  G11C29/028 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1575 ,  H03M13/6502

摘要： A system and method of providing error tolerant memory access operations on a memory device. A method is disclosed including: providing location information of weak memory cells, wherein the location information includes addresses grouped into tiered sets, wherein each tiered set includes addresses having a number of weak memory cells; receiving a target address for a memory read operation; reading data from a virtual repair memory if the target address belongs to a first tiered set of addresses having a number of weak memory cells exceeding a threshold; and if the target address does not belong the first tiered set of addresses, reading data from the memory device and alternatively performing (a) an error correction and error detection (ECED) operation and (b) a target address look up operation, at different settings, until an error free result is obtained.

公开(公告)号：US10002656B2

公开(公告)日：2018-06-19

申请号：US15138318

申请日：2016-04-26

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Munehiro Kozuma

IPC分类号： G11C7/16 ,  G11C11/24 ,  G11C16/04 ,  G11C16/10 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  H01L27/1156 ,  G11C27/00 ,  G11C27/02 ,  G11C11/40 ,  H01L21/02 ,  H01L23/528 ,  H01L27/105 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC分类号： G11C11/24 ,  G11C7/16 ,  G11C11/40 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0441 ,  G11C16/10 ,  G11C27/005 ,  G11C27/02 ,  G11C27/024 ,  H01L21/02565 ,  H01L21/0262 ,  H01L23/528 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

摘要： A semiconductor device capable of generating a signal (e.g., a potential signal or a current signal) suitable for usage environment or a purpose. The semiconductor device includes a first memory circuit, a first circuit, and a second memory circuit. The first circuit converts a digital signal input from the first memory circuit into an analog signal. The first memory circuit includes an input node, an output node, a transistor, and a capacitor. The capacitor is electrically connected to the output node. The transistor can control a conduction state between the input node and the output node. An analog signal is input to the input node from the first circuit. The transistor includes an oxide semiconductor layer where a channel formation region is formed.

公开(公告)号：US09940457B2

公开(公告)日：2018-04-10

申请号：US14621506

申请日：2015-02-13

申请人： International Business Machines Corporation

发明人： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC分类号： G06F21/55 ,  G06F11/07 ,  G11C7/24 ,  G11C11/40 ,  G11C29/04

CPC分类号： G06F21/554 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G06F2221/034 ,  G11C7/24 ,  G11C11/40 ,  G11C2029/0411

摘要： Embodiments of the present disclosure provide a method, computer program product, and system for monitoring a dynamic random-access memory (DRAM) device to detect and respond to a cryogenic attack. A processor receives a set of memory information about a DRAM device. The processor then determines a set of error indicators by processing the memory information using a set of decision parameters. The error indicators are then compared to an attack syndrome to determine if the DRAM is experiencing a cryogenic attack. If the DRAM is experiencing a cryogenic attack, access to the DRAM device is disabled.