公开(公告)号：US20140133254A1

公开(公告)日：2014-05-15

申请号：US14060808

申请日：2013-10-23

申请人： Chiho KIM ,  Zhiliang XIA ,  Sung Hee LEE ,  Nara KIM ,  Dae Sin KIM

发明人： Chiho KIM ,  Zhiliang XIA ,  Sung Hee LEE ,  Nara KIM ,  Dae Sin KIM

IPC分类号： G11C29/08

CPC分类号： G11C29/50016 ,  G11C11/40 ,  G11C29/50 ,  G11C29/56

摘要： A test method of a semiconductor device and a semiconductor test apparatus. The test method includes providing a semiconductor device including a substrate having an active region and an isolation region, a volatile device cell including a gate insulation layer and a gate on the active region, a junction region in the active region, a capacitor connected to the junction region, and a passing gate on the isolation region, providing a first test voltage to the gate and a second test voltage greater than the first test voltage to the passing gate to deteriorate interfacial defects of the gate insulation layer, and measuring retention characteristics of the volatile device cell.

摘要翻译： 半导体器件和半导体测试装置的测试方法。 测试方法包括提供包括具有有源区和隔离区的衬底的半导体器件，在有源区上包括栅极绝缘层和栅极的易失性器件单元，有源区中的结区，连接到 并且在隔离区域上具有通过栅极，向栅极提供第一测试电压，并且对通过栅极提供大于第一测试电压的第二测试电压，以降低栅极绝缘层的界面缺陷，并测量保留特性 易失性器件单元。