公开(公告)号：US20140133254A1

公开(公告)日：2014-05-15

申请号：US14060808

申请日：2013-10-23

申请人： Chiho KIM ,  Zhiliang XIA ,  Sung Hee LEE ,  Nara KIM ,  Dae Sin KIM

发明人： Chiho KIM ,  Zhiliang XIA ,  Sung Hee LEE ,  Nara KIM ,  Dae Sin KIM

IPC分类号： G11C29/08

CPC分类号： G11C29/50016 ,  G11C11/40 ,  G11C29/50 ,  G11C29/56

摘要： A test method of a semiconductor device and a semiconductor test apparatus. The test method includes providing a semiconductor device including a substrate having an active region and an isolation region, a volatile device cell including a gate insulation layer and a gate on the active region, a junction region in the active region, a capacitor connected to the junction region, and a passing gate on the isolation region, providing a first test voltage to the gate and a second test voltage greater than the first test voltage to the passing gate to deteriorate interfacial defects of the gate insulation layer, and measuring retention characteristics of the volatile device cell.

摘要翻译： 半导体器件和半导体测试装置的测试方法。 测试方法包括提供包括具有有源区和隔离区的衬底的半导体器件，在有源区上包括栅极绝缘层和栅极的易失性器件单元，有源区中的结区，连接到 并且在隔离区域上具有通过栅极，向栅极提供第一测试电压，并且对通过栅极提供大于第一测试电压的第二测试电压，以降低栅极绝缘层的界面缺陷，并测量保留特性 易失性器件单元。

公开(公告)号：US20140246782A1

公开(公告)日：2014-09-04

申请号：US14141947

申请日：2013-12-27

申请人： Jiyoung KIM ,  Daeik KIM ,  Kang-Uk KIM ,  Nara KIM ,  Jemin PARK ,  Kyuhyun LEE ,  Hyun-Woo CHUNG ,  Gyoyoung JIN ,  HyeongSun HONG ,  Yoosang HWANG

发明人： Jiyoung KIM ,  Daeik KIM ,  Kang-Uk KIM ,  Nara KIM ,  Jemin PARK ,  Kyuhyun LEE ,  Hyun-Woo CHUNG ,  Gyoyoung JIN ,  HyeongSun HONG ,  Yoosang HWANG

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/10897 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/1464 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface, forming an alignment key and a connection contact that penetrate a portion of the semiconductor substrate and extend from the first surface toward the second surface, forming a first circuit on the first surface of the semiconductor substrate such that the first circuit is electrically connected to the connection contact, recessing the second surface of the semiconductor substrate to form a third surface exposing the alignment key and the connection contact, and forming a second circuit on the third surface of the semiconductor substrate such that the second circuit is electrically connected to the connection contact.

摘要翻译： 一种制造半导体器件的方法包括提供具有第一表面和与第一表面相对的第二表面的半导体衬底，形成对准键和穿过半导体衬底的一部分并从第一表面延伸到第二表面的连接触点 在所述半导体衬底的所述第一表面上形成第一电路，使得所述第一电路电连接到所述连接触点，使所述半导体衬底的所述第二表面凹陷以形成暴露所述对准键和所述连接触点的第三表面，以及 在半导体衬底的第三表面上形成第二电路，使得第二电路电连接到连接触点。