-
1.发明授权Mask pattern verification apparatus, mask pattern verification method and method of fabricating a semiconductor device 有权掩模图案验证装置，掩模图案验证方法以及制造半导体器件的方法公开(公告)号：US08110413B2
公开(公告)日：2012-02-07
申请号：US12880487
申请日：2010-09-13
CPC分类号： G03F1/36 , Y10T29/49117
摘要： In one embodiment, a mask pattern verification apparatus is disclosed. The mask pattern verification apparatus can include a library registration portion registered a clean circuit pattern, a memory portion saved a design circuit pattern, a verification circuit pattern, a verification mask pattern, and a verification wafer pattern, a mask verification portion performing mask verification to the verification mask pattern, a lithography verification portion performing lithography verification to the verification wafer pattern, and a CPU including a library registration circuit registering the clean circuit pattern to the library registration portion, a pattern matching circuit verifying the clean circuit pattern being set or not in the design circuit pattern, a verification pattern extraction circuit extracting the verification circuit pattern from the design circuit pattern, an OPC circuit performing OPC to the verification circuit pattern, a mask verification circuit controlling the mask verification portion, and a lithography verification circuit controlling the lithography verification portion.
摘要翻译： 在一个实施例中，公开了一种掩模图案验证装置。 掩模图案验证装置可以包括登记清洁电路图案的库登记部分，保存设计电路图案的存储部分，验证电路图案，验证掩模图案和验证晶片图案，进行掩模验证的掩模验证部分 验证掩模图案，对验证晶片图案执行光刻验证的光刻验证部分和包括将清洁电路图案注册到库登记部分的库登记电路的CPU，验证清除电路图案被设置的模式匹配电路 在设计电路图案中，从设计电路图案提取验证电路图案的验证图案提取电路，对验证电路图案执行OPC的OPC电路，控制掩模验证部分的掩模验证电路以及光刻验证电路控制 光刻验证部分。
-
2.发明申请MASK PATTERN VERIFICATION APPARATUS, MASK PATTERN VERIFICATION METHOD AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 有权掩模图案验证装置，掩模图案验证方法和制造半导体器件的方法公开(公告)号：US20110086515A1
公开(公告)日：2011-04-14
申请号：US12880487
申请日：2010-09-13
CPC分类号： G03F1/36 , Y10T29/49117
摘要： In one embodiment, a mask pattern verification apparatus is disclosed. The mask pattern verification apparatus can include a library registration portion registered a clean circuit pattern, a memory portion saved a design circuit pattern, a verification circuit pattern, a verification mask pattern, and a verification wafer pattern, a mask verification portion performing mask verification to the verification mask pattern, a lithography verification portion performing lithography verification to the verification wafer pattern, and a CPU including a library registration circuit registering the clean circuit pattern to the library registration portion, a pattern matching circuit verifying the clean circuit pattern being set or not in the design circuit pattern, a verification pattern extraction circuit extracting the verification circuit pattern from the design circuit pattern, an OPC circuit performing OPC to the verification circuit pattern, a mask verification circuit controlling the mask verification portion, and a lithography verification circuit controlling the lithography verification portion.
摘要翻译： 在一个实施例中，公开了一种掩模图案验证装置。 掩模图案验证装置可以包括登记清洁电路图案的库登记部分，保存设计电路图案的存储部分，验证电路图案，验证掩模图案和验证晶片图案，进行掩模验证的掩模验证部分 验证掩模图案，对验证晶片图案执行光刻验证的光刻验证部分和包括将清洁电路图案注册到库登记部分的库登记电路的CPU，验证清除电路图案被设置的模式匹配电路 在设计电路图案中，从设计电路图案提取验证电路图案的验证图案提取电路，对验证电路图案执行OPC的OPC电路，控制掩模验证部分的掩模验证电路以及光刻验证电路控制 光刻验证部分。
-
搜索结果
2 条记录 (耗时 0.018 秒)
