公开(公告)号：US20110086515A1

公开(公告)日：2011-04-14

申请号：US12880487

申请日：2010-09-13

申请人： Chikaaki KODAMA ,  Takanori Urakami ,  Nozomu Furuta ,  Shunsuke Kagaya

发明人： Chikaaki KODAMA ,  Takanori Urakami ,  Nozomu Furuta ,  Shunsuke Kagaya

IPC分类号： H01L21/31 ,  G06F17/50

CPC分类号： G03F1/36 ,  Y10T29/49117

摘要： In one embodiment, a mask pattern verification apparatus is disclosed. The mask pattern verification apparatus can include a library registration portion registered a clean circuit pattern, a memory portion saved a design circuit pattern, a verification circuit pattern, a verification mask pattern, and a verification wafer pattern, a mask verification portion performing mask verification to the verification mask pattern, a lithography verification portion performing lithography verification to the verification wafer pattern, and a CPU including a library registration circuit registering the clean circuit pattern to the library registration portion, a pattern matching circuit verifying the clean circuit pattern being set or not in the design circuit pattern, a verification pattern extraction circuit extracting the verification circuit pattern from the design circuit pattern, an OPC circuit performing OPC to the verification circuit pattern, a mask verification circuit controlling the mask verification portion, and a lithography verification circuit controlling the lithography verification portion.

摘要翻译： 在一个实施例中，公开了一种掩模图案验证装置。 掩模图案验证装置可以包括登记清洁电路图案的库登记部分，保存设计电路图案的存储部分，验证电路图案，验证掩模图案和验证晶片图案，进行掩模验证的掩模验证部分 验证掩模图案，对验证晶片图案执行光刻验证的光刻验证部分和包括将清洁电路图案注册到库登记部分的库登记电路的CPU，验证清除电路图案被设置的模式匹配电路 在设计电路图案中，从设计电路图案提取验证电路图案的验证图案提取电路，对验证电路图案执行OPC的OPC电路，控制掩模验证部分的掩模验证电路以及光刻验证电路控制 光刻验证部分。

公开(公告)号：US20130164934A1

公开(公告)日：2013-06-27

申请号：US13665803

申请日：2012-10-31

申请人： Kosuke YANAGIDAIRA ,  Chikaaki KODAMA

发明人： Kosuke YANAGIDAIRA ,  Chikaaki KODAMA

IPC分类号： H01L21/768

CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

公开(公告)号：US20120184109A1

公开(公告)日：2012-07-19

申请号：US13397750

申请日：2012-02-16

申请人： Hiromitsu MASHITA ,  Toshiya KOTANI ,  Fumiharu NAKAJIMA ,  Takafumi TAGUCHI ,  Chikaaki KODAMA

发明人： Hiromitsu MASHITA ,  Toshiya KOTANI ,  Fumiharu NAKAJIMA ,  Takafumi TAGUCHI ,  Chikaaki KODAMA

IPC分类号： H01L21/302

CPC分类号： H01L21/0337

摘要： A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.

摘要翻译： 通过多次执行图案变换步骤来形成图案的半导体器件的制造方法包括：在多个图案变换步骤中，基于可能的总量，在每个连续的两个图案变换步骤中设定要形成的图案的完成图案尺寸 在连续的两个图案变换步骤中要形成的图案的平面尺寸变化。

公开(公告)号：US20100021825A1

公开(公告)日：2010-01-28

申请号：US12478479

申请日：2009-06-04

申请人： Chikaaki KODAMA ,  Hirotaka Ichikawa ,  Kazuyuki Masukawa ,  Toshiya Kotani

发明人： Chikaaki KODAMA ,  Hirotaka Ichikawa ,  Kazuyuki Masukawa ,  Toshiya Kotani

IPC分类号： G03F1/00

CPC分类号： G03F1/36

摘要： A mask pattern data creation method includes: determining whether or not a spacing of adjacent assist pattern feature data is not more than a prescribed spacing, based on: initial position data indicating an initially set position of the assist pattern feature data determined based on an illumination condition; and initial size data indicating an initially set size of the assist pattern feature data satisfying a size condition to not optically form an image on the transfer destination; and moving at least one of the adjacent assist pattern feature data or reducing a size of the at least one to increase the spacing of the assist pattern feature data to exceed a prescribed spacing in the case where it is determined that the spacing of the assist pattern feature data is not more than the prescribed spacing.

摘要翻译： 掩模图案数据创建方法包括：基于：基于指示基于照明确定的辅助图案特征数据的初始设置位置的初始位置数据来确定相邻辅助图案特征数据的间隔是否不大于规定间距 条件; 以及初始尺寸数据，其指示辅助图案特征数据的初始设置尺寸，其满足不在转印目的地上光学地形成图像的尺寸条件; 以及在确定所述辅助图案的间距的情况下，移动所述相邻辅助图案特征数据中的至少一个或减小所述至少一个的尺寸以增加所述辅助图案特征数据的间隔超过规定间隔 特征数据不超过规定的间距。

公开(公告)号：US20100003819A1

公开(公告)日：2010-01-07

申请号：US12491129

申请日：2009-06-24

申请人： Takafumi TAGUCHI ,  Toshiya KOTANI ,  Hiromitsu MASHITA ,  Fumiharu NAKAJIMA ,  Chikaaki KODAMA

发明人： Takafumi TAGUCHI ,  Toshiya KOTANI ,  Hiromitsu MASHITA ,  Fumiharu NAKAJIMA ,  Chikaaki KODAMA

IPC分类号： H01L21/02 ,  G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  G06F2217/12 ,  H01L27/118 ,  Y02P90/265

摘要： A design layout data creating method includes creating design layout data of a semiconductor device such that patterns formed on a wafer when patterns corresponding to the design layout data are formed on the wafer have a pattern coverage ratio within a predetermined range in a wafer surface and total peripheral length of the patterns formed on the wafer when the patterns corresponding to the design layout are formed on the wafer is pattern peripheral length within a predetermined range.

摘要翻译： 设计布局数据创建方法包括：创建半导体器件的设计布局数据，使得当在晶片上形成对应于设计布局数据的图案时，在晶片上形成的图案具有在晶片表面的预定范围内的图案覆盖率，并且总计 当在晶片上形成对应于设计布局的图案时，在晶片上形成的图案的周长长度在预定范围内。

公开(公告)号：US20130062771A1

公开(公告)日：2013-03-14

申请号：US13405922

申请日：2012-02-27

申请人： Chikaaki KODAMA ,  Koichi Nakayama ,  Toshiya Kotani ,  Shigeki Nojima

发明人： Chikaaki KODAMA ,  Koichi Nakayama ,  Toshiya Kotani ,  Shigeki Nojima

IPC分类号： H01L23/48 ,  H01L21/311 ,  G06F17/50

CPC分类号： H01L21/31144 ,  G06F17/5077 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.

公开(公告)号：US20120183906A1

公开(公告)日：2012-07-19

申请号：US13237651

申请日：2011-09-20

申请人： Chikaaki KODAMA ,  Toshiya Kotani ,  Hiromitusu Mashita ,  Fumiharu Nakajima

发明人： Chikaaki KODAMA ,  Toshiya Kotani ,  Hiromitusu Mashita ,  Fumiharu Nakajima

IPC分类号： G03F7/20 ,  G06F17/50

CPC分类号： G03F1/36 ,  G03F1/38

摘要： According to a mask pattern generating method of the embodiments, an undesired pattern, which is transferred onto a substrate due to an auxiliary pattern when an on-substrate pattern is formed on the substrate by using a mask pattern in which the auxiliary pattern is placed, is extracted as an undesired transfer pattern. Then, the mask pattern is corrected by changing a size of the auxiliary pattern according to a size and a position of the undesired transfer pattern.

摘要翻译： 根据实施例的掩模图案生成方法，当通过使用其中放置辅助图案的掩模图案在衬底上形成衬底上图案时，由于辅助图案而转移到衬底上的不需要的图案， 被提取为不期望的转移模式。 然后，通过根据不希望的转印图案的尺寸和位置改变辅助图案的尺寸来校正掩模图案。

公开(公告)号：US20110307845A1

公开(公告)日：2011-12-15

申请号：US13050864

申请日：2011-03-17

申请人： Takafumi TAGUCHI ,  Toshiya KOTANI ,  Hiromitsu MASHITA ,  Fumiharu NAKAJIMA ,  Ryota ABURADA ,  Chikaaki KODAMA

发明人： Takafumi TAGUCHI ,  Toshiya KOTANI ,  Hiromitsu MASHITA ,  Fumiharu NAKAJIMA ,  Ryota ABURADA ,  Chikaaki KODAMA

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position.

摘要翻译： 根据一个实施例的图案尺寸计算方法计算当在形成在基板上的电路图案的上层中处理电路图案时用作掩模的掩模构件的锥形形状。 该方法基于锥形形状从电路图案上的形状预测位置计算面向掩模构件的打开角度。 该方法根据在形状预测位置处形成的打开角度来计算电路图案的尺寸。

公开(公告)号：US20110294239A1

公开(公告)日：2011-12-01

申请号：US13051961

申请日：2011-03-18

申请人： Chikaaki KODAMA ,  Toshiya Kotani ,  Shigeki Nojima ,  Shoji Mimotogi

发明人： Chikaaki KODAMA ,  Toshiya Kotani ,  Shigeki Nojima ,  Shoji Mimotogi

IPC分类号： H01L21/66 ,  G06F17/50

CPC分类号： G03F1/36

摘要： According to a sub-resolution assist feature arranging method in embodiments, it is selected which of a rule base and a model base is set for which pattern region on pattern data corresponding to a main pattern as a type of the method of arranging the sub-resolution assist feature for improving resolution of the main pattern formed on a substrate. Then, the sub-resolution assist feature by the rule base is arranged in a pattern region set as the rule base and the sub-resolution assist feature by the model base is arranged in a pattern region set as the model base.

摘要翻译： 根据实施例中的子分辨率辅助特征排列方法，选择规则库和模型库中的哪一个被设置为对应于主图案的图案数据上的哪个图案区域作为安排子图形的方法的类型， 分辨率辅助功能，用于提高在基板上形成的主图案的分辨率。 然后，将规则库的子分辨率辅助特征设置在设置为规则库的图案区域中，并且由模型库将子分辨率辅助特征排列在设置为模型库的图案区域中。

公开(公告)号：US20110069531A1

公开(公告)日：2011-03-24

申请号：US12858986

申请日：2010-08-18

申请人： Ryota ABURADA ,  Toshiya KOTANI ,  Takafumi TAGUCHI ,  Chikaaki KODAMA

发明人： Ryota ABURADA ,  Toshiya KOTANI ,  Takafumi TAGUCHI ,  Chikaaki KODAMA

IPC分类号： G11C11/00 ,  H01L21/02

CPC分类号： H01L27/2481 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/22 ,  G11C13/0004 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1675

摘要： According to one embodiment, a method of manufacturing a nonvolatile semiconductor storage device includes a memory-cell forming step, a first wire forming step, and a second wire forming step. The memory-cell forming step is forming dummy memory cells arranged at a predetermined space apart from an end memory cell located at an end of a group of memory cells set in contact with the same first or second wire among the memory cells, the dummy memory cells having a laminated structure same as that of the memory cells and being set in contact with no second wire.

摘要翻译： 根据一个实施例，制造非易失性半导体存储装置的方法包括存储单元形成步骤，第一线形成步骤和第二线形成步骤。 存储单元形成步骤是形成布置在与存储单元中的与相同的第一或第二布线接触的一组存储单元的一端的端部存储单元隔开的预定空间的虚拟存储单元，该虚拟存储器 电池具有与存储单元的层叠结构相同的层叠结构，并与第二导线接触。