公开(公告)号：US09032162B1

公开(公告)日：2015-05-12

申请号：US13209137

申请日：2011-08-12

申请人： Ching-Chi Chang ,  Ravish Kapasi ,  Jeffrey Schulz ,  Michael H. M. Chu ,  Caroline Ssu-Min Chen ,  Chiakang Sung

发明人： Ching-Chi Chang ,  Ravish Kapasi ,  Jeffrey Schulz ,  Michael H. M. Chu ,  Caroline Ssu-Min Chen ,  Chiakang Sung

IPC分类号： G11C7/10

CPC分类号： G11C7/1075 ,  G06F13/161

摘要： An integrated circuit may include a memory controller serving as an interface between master processing modules and system memory. The master processing modules may provide memory access requests to the memory controller along with respective tag identifications. The memory controller may place the memory access requests in a queue for fulfillment. The memory controller may include a merging module that generates a memory access request to replace two or more memory access requests previously received from the master processing modules. The merging module may store information associated with the memory access requests that were merged and use the stored information to assign appropriate tag identifications to portions of data obtained from system memory when fulfilling the generated memory access request. The memory controller may include a verification module that can be used with test equipment to optimize the design of the master processing modules for improved memory access performance.

摘要翻译： 集成电路可以包括用作主处理模块和系统存储器之间的接口的存储器控​​制器。 主处理模块可以向存储器控制器提供存储器访问请求以及相应的标签标识。 存储器控制器可以将存储器访问请求放置在队列中以实现。 存储器控制器可以包括合并模块，其生成存储器访问请求以替换先前从主处理模块接收的两个或多个存储器访问请求。 合并模块可以存储与被合并的存储器访问请求相关联的信息，并使用所存储的信息，以在满足生成的存储器访问请求时从系统存储器获得的数据部分分配适当的标签标识。 存储器控制器可以包括可与测试设备一起使用的验证模块，以优化主处理模块的设计以改善存储器访问性能。

公开(公告)号：USD369870S

公开(公告)日：1996-05-14

申请号：US35745

申请日：1995-03-06

申请人： Ching-Chi Chang

设计人： Ching-Chi Chang

公开(公告)号：US09244867B1

公开(公告)日：2016-01-26

申请号：US13151123

申请日：2011-06-01

申请人： Jeffrey Schulz ,  Ching-Chi Chang ,  Caroline Ssu-Min Chen

发明人： Jeffrey Schulz ,  Ching-Chi Chang ,  Caroline Ssu-Min Chen

IPC分类号： G06F12/00 ,  G06F13/14 ,  G06F13/00

CPC分类号： G06F13/14 ,  G06F12/00

摘要： A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have predetermined bit widths. To provide the memory controller with adjustable port widths, a mapping interface may be provided that interfaces between master processing modules and the memory controller. The mapping interface may allocate port resources such as read data ports and write data ports of the memory controller to each master processing module. The mapping interface may assign a desirable number of read data ports and write data ports to each master to accommodate the requirements of that master. The mapping interface may assign a command port to each master that receives memory access requests from that master. The mapping interface may convey write acknowledgements in response to fulfilling write access requests.

摘要翻译： 可编程集成电路可以具有在主模块和系统存储器之间进行接口的存储器控​​制器。 存储器控制器可以经由具有预定位宽的端口从主机接收存储器访问请求。 为了向存储器控制器提供可调整的端口宽度，可以提供在主处理模块和存储器控制器之间进行接口的映射接口。 映射接口可以向每个主处理模块分配诸如读数据端口和存储器控制器的写数据端口的端口资源。 映射界面可以分配理想数量的读取数据端口并将数据端口写入每个主机以适应该主机的要求。 映射接口可以向从主机接收存储器访问请求的每个主机分配一个命令端口。 响应于满足的写访问请求，映射界面可以传送写确认。

公开(公告)号：US08930641B1

公开(公告)日：2015-01-06

申请号：US13160384

申请日：2011-06-14

申请人： Ravish Kapasi ,  Jeffrey Schulz ,  Ching-Chi Chang ,  Caroline Ssu-Min Chen

发明人： Ravish Kapasi ,  Jeffrey Schulz ,  Ching-Chi Chang ,  Caroline Ssu-Min Chen

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/28

摘要： An integrated circuit may have a memory controller that interfaces between master processing modules and system memory. A scheduling module may be used to handle memory access requests received from multiple master modules. The scheduling module may arrange the received memory access requests in an order for fulfillment with system memory. A bypass module may be used to provide a low latency bypass path that allows memory access requests to bypass the scheduling module. The bypass module may include an eligibility detection module that identifies memory access requests eligible for scheduler bypassing, a port selection module that provides a low latency bypass path for the eligible memory access requests, multiplexing circuitry that selects between memory access requests provided from the low latency bypass path and from the output of the scheduling module, and a masking module that prevents redundant fulfillment of memory access requests.

摘要翻译： 集成电路可以具有在主处理模块和系统存储器之间进行接口的存储器控​​制器。 调度模块可用于处理从多个主模块接收到的存储器访问请求。 调度模块可以以系统存储器的顺序来排列所接收的存储器访问请求。 旁路模块可用于提供允许存储器访问请求绕过调度模块的低延迟旁路路径。 旁路模块可以包括标识符合调度器旁路的存储器访问请求的资格检测模块，为合格存储器访问请求提供低延迟旁路路径的端口选择模块，从低延迟提供的存储器访问请求之间进行选择的复用电路 旁路路径和调度模块的输出，以及防止冗余实现存储器访问请求的掩蔽模块。