公开(公告)号：US09558131B1

公开(公告)日：2017-01-31

申请号：US13164426

申请日：2011-06-20

申请人： Jeffrey Schulz ,  Chiakang Sung ,  Michael H. M. Chu

发明人： Jeffrey Schulz ,  Chiakang Sung ,  Michael H. M. Chu

IPC分类号： G06F13/00

CPC分类号： G06F13/00 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/4022

摘要： An IC that includes a first memory controller, a second memory controller, and a first bonding circuit coupled to the first memory controller, where the first bonding circuit is a hard logic bonding circuit and is operable to coordinate memory control functions of the first memory controller and the second memory controller. In one implementation, the first memory controller is an N bits wide memory controller, the second memory controller is an M bits wide memory controller, and the first bonding circuit is operable to coordinate the memory control functions of the first memory controller and the second memory controller such that the first and second memory controllers together function as an N+M bits wide memory controller, where N and M are positive integers.

摘要翻译： 一种IC，包括第一存储器控制器，第二存储器控制器和耦合到第一存储器控制器的第一接合电路，其中第一接合电路是硬逻辑接合电路，并且可操作以协调第一存储器控制器的存储器控​​制功能 和第二存储器控制器。 在一个实现中，第一存储器控制器是N位宽存储器控制器，第二存储器控制器是M位宽存储器控制器，并且第一接合电路可操作以协调第一存储器控制器和第二存储器的存储器控​​制功能 控制器，使得第一和第二存储器控制器一起用作N + M位宽存储器控制器，其中N和M是正整数。

公开(公告)号：US09032162B1

公开(公告)日：2015-05-12

申请号：US13209137

申请日：2011-08-12

申请人： Ching-Chi Chang ,  Ravish Kapasi ,  Jeffrey Schulz ,  Michael H. M. Chu ,  Caroline Ssu-Min Chen ,  Chiakang Sung

发明人： Ching-Chi Chang ,  Ravish Kapasi ,  Jeffrey Schulz ,  Michael H. M. Chu ,  Caroline Ssu-Min Chen ,  Chiakang Sung

IPC分类号： G11C7/10

CPC分类号： G11C7/1075 ,  G06F13/161

摘要： An integrated circuit may include a memory controller serving as an interface between master processing modules and system memory. The master processing modules may provide memory access requests to the memory controller along with respective tag identifications. The memory controller may place the memory access requests in a queue for fulfillment. The memory controller may include a merging module that generates a memory access request to replace two or more memory access requests previously received from the master processing modules. The merging module may store information associated with the memory access requests that were merged and use the stored information to assign appropriate tag identifications to portions of data obtained from system memory when fulfilling the generated memory access request. The memory controller may include a verification module that can be used with test equipment to optimize the design of the master processing modules for improved memory access performance.

摘要翻译： 集成电路可以包括用作主处理模块和系统存储器之间的接口的存储器控​​制器。 主处理模块可以向存储器控制器提供存储器访问请求以及相应的标签标识。 存储器控制器可以将存储器访问请求放置在队列中以实现。 存储器控制器可以包括合并模块，其生成存储器访问请求以替换先前从主处理模块接收的两个或多个存储器访问请求。 合并模块可以存储与被合并的存储器访问请求相关联的信息，并使用所存储的信息，以在满足生成的存储器访问请求时从系统存储器获得的数据部分分配适当的标签标识。 存储器控制器可以包括可与测试设备一起使用的验证模块，以优化主处理模块的设计以改善存储器访问性能。

公开(公告)号：US07593273B2

公开(公告)日：2009-09-22

申请号：US11935310

申请日：2007-11-05

申请人： Michael H. M. Chu ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Andrew Bellis ,  Philip Clarke ,  Manoj B. Roge

发明人： Michael H. M. Chu ,  Joseph Huang ,  Chiakang Sung ,  Yan Chong ,  Andrew Bellis ,  Philip Clarke ,  Manoj B. Roge

IPC分类号： G11C7/10

CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  H03L7/06 ,  H03L7/0812

摘要： Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

摘要翻译： 用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。 一个例子是通过在输入和电路之间使用重新定时元件实现这一点。 重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。 平均接收无差错数据的最小和最大延迟。 然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。 在一个示例中，输入信号可以被延迟与延迟设置相对应的量。 在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。

公开(公告)号：US07589556B1

公开(公告)日：2009-09-15

申请号：US11925717

申请日：2007-10-26

申请人： Johnson Tan ,  Andrew Bellis ,  Philip Clarke ,  Yan Chong ,  Joseph Huang ,  Michael H. M. Chu ,  Chiakang Sung

发明人： Johnson Tan ,  Andrew Bellis ,  Philip Clarke ,  Yan Chong ,  Joseph Huang ,  Michael H. M. Chu ,  Chiakang Sung

IPC分类号： G06F7/38

CPC分类号： H03M9/00 ,  H03K5/131 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00058

摘要： Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and output circuits to self-calibrate by compensating for temperature and voltage changes in an efficient manner, without the need for device reconfiguration. Calibration settings can be maintained while new calibration settings are loaded. Skew between clock and data signals, as well as among multiple data signals, can be reduced. Dynamic control is achieved while consuming only a minimal resources including route paths.

摘要翻译： 用于动态控制校准数据的电路，方法和装置，用于调整集成电路上的输入和输出信号的时序。 该动态控制允许输入和输出电路通过以有效的方式补偿温度和电压变化而进行自校准，而不需要对器件重新配置。 加载新的校准设置时，可以保持校准设置。 可以减少时钟和数据信号之间以及多个数据信号之间的偏移。 实现动态控制，同时仅消耗包括路由路径在内的最小资源。

公开(公告)号：US09343124B1

公开(公告)日：2016-05-17

申请号：US13194842

申请日：2011-07-29

申请人： Caroline Ssu-Min Chen ,  Jeffrey Schulz ,  Michael H. M. Chu ,  Ravish Kapasi

发明人： Caroline Ssu-Min Chen ,  Jeffrey Schulz ,  Michael H. M. Chu ,  Ravish Kapasi

IPC分类号： G06F12/00 ,  G11C7/10 ,  G06F12/08

CPC分类号： G11C7/1075 ,  G06F12/0853

摘要： A method and system for operating a multi-port memory system are disclosed. A memory controller may service read requests by accessing requested data from an external memory and communicating it to the requesting memory ports for access by devices coupled to the memory ports. A shared memory of the memory controller may be used to temporarily store data if a buffer associated with a requesting device is full. To reduce the ability for a slower memory port to occupy the shared memory and cause faster memory ports to be underserviced, the memory controller may advantageously regulate or limit issuance of read requests by memory ports operating at slower clock frequencies. The memory ports may be regulated independently of one another based on at least one respective attribute of each memory port, at least one attribute of the external memory, etc.

摘要翻译： 公开了一种用于操作多端口存储器系统的方法和系统。 存储器控制器可以通过从外部存储器访问所请求的数据并将其传送到请求存储器端口来服务读取请求以供由耦合到存储器端口的设备访问。 如果与请求设备相关联的缓冲器已满，则可以使用存储器控制器的共享存储器临时存储数据。 为了减少较慢的存储器端口占用共享存储器并导致更快的存储器端口不足的能力，存储器控制器可以有利地调节或限制以更慢的时钟频率操作的存储器端口发出读取请求。 存储器端口可以基于每个存储器端口的至少一个相应属性，外部存储器的至少一个属性等彼此独立地被调整。

公开(公告)号：US08671303B2

公开(公告)日：2014-03-11

申请号：US13349228

申请日：2012-01-12

申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

公开(公告)号：US08122275B2

公开(公告)日：2012-02-21

申请号：US11843123

申请日：2007-08-22

申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H. M. Chu

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。

公开(公告)号：US07990783B1

公开(公告)日：2011-08-02

申请号：US13004136

申请日：2011-01-11

申请人： Philip Clarke ,  Andrew Bellis ,  Yan Chong ,  Joseph Huang ,  Michael H. M. Chu

发明人： Philip Clarke ,  Andrew Bellis ,  Yan Chong ,  Joseph Huang ,  Michael H. M. Chu

IPC分类号： G11C7/00 ,  H03K19/00 ,  H03K5/12

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

摘要： Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.

摘要翻译： 将输入寄存器与DQS信号上的虚假转换隔离的电路，方法和设备。 一个示例从核心接收使能信号。 可以称为半周期电路的逻辑电路将其前端的使能脉冲缩短半个周期。 缩短的使能信号被传递到诸如寄存器的存储元件。 缩短的使能信号的有效脉冲清除寄存器，其提供闭合开关的控制信号，例如与门。 当开关闭合时，开关将DQS信号传送到输入寄存器，并在断开时将输入寄存器与DQS信号隔离。 缩短的使能信号防止开关在DQS信号的早期打开和传递寄生跳变，例如在背对背非连续读取周期期间。

公开(公告)号：US07928770B1

公开(公告)日：2011-04-19

申请号：US11935347

申请日：2007-11-05

申请人： Andrew Bellis ,  Philip Clarke ,  Joseph Huang ,  Yan Chong ,  Michael H. M. Chu ,  Manoj B. Roge

发明人： Andrew Bellis ,  Philip Clarke ,  Joseph Huang ,  Yan Chong ,  Michael H. M. Chu ,  Manoj B. Roge

IPC分类号： H03K19/096

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18

摘要： I/O blocks include input, output, and output enable circuits for interfacing with memory devices. The input circuit includes registers for capturing a double data rate signal, converting it into single data rate signals, and resynchronizing the single data rate signals. Multiple devices may be accessible with each device potentially having a different clock signal for resynchronizing. Another clock signal may be used to align/synchronize resulting signals from multiple devices. The resynchronized single rate signals can be converted into half-rate data signals, and the four half-rate data signals can be provided to resources in the programmable device core. The input circuit also may provide a half-rate clock signal synchronized with the half-rate data signals to the programmable device core. The half rate clock signal can be derived from the full-rate clock signal using a data strobe signal, a full-rate clock signal, or a half-rate clock signal as an input.

摘要翻译： I / O块包括用于与存储器件连接的输入，输出和输出使能电路。 输入电路包括用于捕获双倍数据速率信号的寄存器，将其转换为单个数据速率信号，并重新同步单个数据速率信号。 多个设备可以被访问，每个设备潜在地具有用于重新同步的不同的时钟信号。 另一个时钟信号可用于对准/同步来自多个设备的结果信号。 再同步的单速率信号可以转换成半速率数据信号，并且可以将四个半速率数据信号提供给可编程器件核心中的资源。 输入电路还可以将半速率数据信号同步的半速率时钟信号提供给可编程器件核心。 半速率时钟信号可以使用数据选通信号，全速率时钟信号或半速率时钟信号作为输入从全速率时钟信号导出。

公开(公告)号：US07876630B1

公开(公告)日：2011-01-25

申请号：US11935405

申请日：2007-11-06

申请人： Philip Clarke ,  Andrew Bellis ,  Yan Chong ,  Joseph Huang ,  Michael H. M. Chu

发明人： Philip Clarke ,  Andrew Bellis ,  Yan Chong ,  Joseph Huang ,  Michael H. M. Chu

IPC分类号： G11C7/00 ,  H03K19/00 ,  H03K5/12

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

摘要： Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.