公开(公告)号：US08359420B2

公开(公告)日：2013-01-22

申请号：US12819451

申请日：2010-06-21

申请人： Ching-Han Tsai ,  Cheng-Lun Chang ,  Jung-Tao Liu ,  Ya-Chau Yang

发明人： Ching-Han Tsai ,  Cheng-Lun Chang ,  Jung-Tao Liu ,  Ya-Chau Yang

IPC分类号： G06F13/28

CPC分类号： G06F15/163 ,  G06F15/17

摘要： An external memory based FIFO (xFIFO) apparatus coupled to an external memory and a register bus is disclosed. The xFIFO apparatus includes an xFIFO engine, a wDMA engine, an rDMA engine, a first virtual FIFO, and a second virtual FIFO. The xFIFO engine receives a FIFO command from the register bus and generates a writing DMA command and a reading DMA command. The wDMA engine receives the writing DMA command from the xFIFO engine and forwards an incoming data to the external memory. The rDMA engine receives the reading DMA command from the xFIFO engine and pre-fetches a FIFO data from the external memory. The wDMA engine and the rDMA engine synchronize with each other via the first virtual FIFO and the second virtual FIFO.

摘要翻译： 公开了一种耦合到外部存储器和寄存器总线的基于外部存储器的FIFO（xFIFO）装置。 xFIFO装置包括xFIFO引擎，wDMA引擎，rDMA引擎，第一虚拟FIFO和第二虚拟FIFO。 xFIFO引擎从寄存器总线接收FIFO命令，并产生写入DMA命令和读取DMA命令。 wDMA引擎从xFIFO引擎接收写入DMA命令，并将传入的数据转发到外部存储器。 rDMA引擎从xFIFO引擎接收读取DMA命令，并从外部存储器中预取FIFO数据。 wDMA引擎和rDMA引擎通过第一虚拟FIFO和第二虚拟FIFO相互同步。

公开(公告)号：US20100325334A1

公开(公告)日：2010-12-23

申请号：US12819451

申请日：2010-06-21

申请人： Ching-Han TSAI ,  Cheng-Lun Chang ,  Jung-Tao Liu ,  Ya-Chau Yang

发明人： Ching-Han TSAI ,  Cheng-Lun Chang ,  Jung-Tao Liu ,  Ya-Chau Yang

IPC分类号： G06F13/28

CPC分类号： G06F15/163 ,  G06F15/17

摘要： An external memory based FIFO (xFIFO) apparatus coupled to an external memory and a register bus is disclosed. The xFIFO apparatus includes an xFIFO engine, a wDMA engine, an rDMA engine, a first virtual FIFO, and a second virtual FIFO. The xFIFO engine receives a FIFO command from the register bus and generates a writing DMA command and a reading DMA command. The wDMA engine receives the writing DMA command from the xFIFO engine and forwards an incoming data to the external memory. The rDMA engine receives the reading DMA command from the xFIFO engine and pre-fetches a FIFO data from the external memory. The wDMA engine and the rDMA engine synchronize with each other via the first virtual FIFO and the second virtual FIFO.

摘要翻译： 公开了一种耦合到外部存储器和寄存器总线的基于外部存储器的FIFO（xFIFO）装置。 xFIFO装置包括xFIFO引擎，wDMA引擎，rDMA引擎，第一虚拟FIFO和第二虚拟FIFO。 xFIFO引擎从寄存器总线接收FIFO命令，并产生写入DMA命令和读取DMA命令。 wDMA引擎从xFIFO引擎接收写入DMA命令，并将传入的数据转发到外部存储器。 rDMA引擎从xFIFO引擎接收读取DMA命令，并从外部存储器中预取FIFO数据。 wDMA引擎和rDMA引擎通过第一虚拟FIFO和第二虚拟FIFO相互同步。

公开(公告)号：US07065491B2

公开(公告)日：2006-06-20

申请号：US10078021

申请日：2002-02-15

申请人： Tsung-Han Tsai ,  Ya-Chau Yang

发明人： Tsung-Han Tsai ,  Ya-Chau Yang

IPC分类号： G10L19/00 ,  H04N7/12 ,  G06F5/00 ,  H03M7/00

CPC分类号： G10L19/16 ,  G10L19/0212

摘要： An inverse-modified discrete cosine transform and overlap-add method, and hardware structure for MPEG Layer3 audio signal decoding. In order to have the MPEG Layer3 audio signal decoder have more competitive power in the consumer market, the present invention provides a low cost fast algorithm of the inverse-modified discrete cosine transform and overlap-add, so that the quantity of the operation needed in the decoding process can be significantly reduced to enhance the system performance. Afterwards, according to the fast algorithm, the present invention provides a hardware structure that is suitable for the inverse-modified discrete cosine transform and overlap-add in the MPEG Layer3 decoder. Since the hardware structure of the present invention makes the MPEG Layer3 decoder able to be implemented by the application specific integrated circuit (ASIC), the entire system can fulfill the low cost and high performance requirements.