公开(公告)号：US20100325334A1

公开(公告)日：2010-12-23

申请号：US12819451

申请日：2010-06-21

申请人： Ching-Han TSAI ,  Cheng-Lun Chang ,  Jung-Tao Liu ,  Ya-Chau Yang

发明人： Ching-Han TSAI ,  Cheng-Lun Chang ,  Jung-Tao Liu ,  Ya-Chau Yang

IPC分类号： G06F13/28

CPC分类号： G06F15/163 ,  G06F15/17

摘要： An external memory based FIFO (xFIFO) apparatus coupled to an external memory and a register bus is disclosed. The xFIFO apparatus includes an xFIFO engine, a wDMA engine, an rDMA engine, a first virtual FIFO, and a second virtual FIFO. The xFIFO engine receives a FIFO command from the register bus and generates a writing DMA command and a reading DMA command. The wDMA engine receives the writing DMA command from the xFIFO engine and forwards an incoming data to the external memory. The rDMA engine receives the reading DMA command from the xFIFO engine and pre-fetches a FIFO data from the external memory. The wDMA engine and the rDMA engine synchronize with each other via the first virtual FIFO and the second virtual FIFO.

摘要翻译： 公开了一种耦合到外部存储器和寄存器总线的基于外部存储器的FIFO（xFIFO）装置。 xFIFO装置包括xFIFO引擎，wDMA引擎，rDMA引擎，第一虚拟FIFO和第二虚拟FIFO。 xFIFO引擎从寄存器总线接收FIFO命令，并产生写入DMA命令和读取DMA命令。 wDMA引擎从xFIFO引擎接收写入DMA命令，并将传入的数据转发到外部存储器。 rDMA引擎从xFIFO引擎接收读取DMA命令，并从外部存储器中预取FIFO数据。 wDMA引擎和rDMA引擎通过第一虚拟FIFO和第二虚拟FIFO相互同步。

公开(公告)号：US08359420B2

公开(公告)日：2013-01-22

申请号：US12819451

申请日：2010-06-21

申请人： Ching-Han Tsai ,  Cheng-Lun Chang ,  Jung-Tao Liu ,  Ya-Chau Yang

发明人： Ching-Han Tsai ,  Cheng-Lun Chang ,  Jung-Tao Liu ,  Ya-Chau Yang

IPC分类号： G06F13/28

CPC分类号： G06F15/163 ,  G06F15/17

摘要： An external memory based FIFO (xFIFO) apparatus coupled to an external memory and a register bus is disclosed. The xFIFO apparatus includes an xFIFO engine, a wDMA engine, an rDMA engine, a first virtual FIFO, and a second virtual FIFO. The xFIFO engine receives a FIFO command from the register bus and generates a writing DMA command and a reading DMA command. The wDMA engine receives the writing DMA command from the xFIFO engine and forwards an incoming data to the external memory. The rDMA engine receives the reading DMA command from the xFIFO engine and pre-fetches a FIFO data from the external memory. The wDMA engine and the rDMA engine synchronize with each other via the first virtual FIFO and the second virtual FIFO.

摘要翻译： 公开了一种耦合到外部存储器和寄存器总线的基于外部存储器的FIFO（xFIFO）装置。 xFIFO装置包括xFIFO引擎，wDMA引擎，rDMA引擎，第一虚拟FIFO和第二虚拟FIFO。 xFIFO引擎从寄存器总线接收FIFO命令，并产生写入DMA命令和读取DMA命令。 wDMA引擎从xFIFO引擎接收写入DMA命令，并将传入的数据转发到外部存储器。 rDMA引擎从xFIFO引擎接收读取DMA命令，并从外部存储器中预取FIFO数据。 wDMA引擎和rDMA引擎通过第一虚拟FIFO和第二虚拟FIFO相互同步。

公开(公告)号：US07707334B2

公开(公告)日：2010-04-27

申请号：US11282531

申请日：2005-11-18

申请人： Lincheng Wang ,  Ching-Han Tsai ,  Cheng-Lun Chang ,  Uma Shankar Durvasula ,  Jau-Wen Ren

发明人： Lincheng Wang ,  Ching-Han Tsai ,  Cheng-Lun Chang ,  Uma Shankar Durvasula ,  Jau-Wen Ren

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F13/4234 ,  G06F2213/0038 ,  H04N21/443

摘要： A forced lock-step operation between a CPU (software) and the hardware is eliminated by unburdening the CPU from monitoring the hardware until it is finished with its task. This is done by providing a data/control message queue into which the CPU writes combined data/control messages and places an End tag into the queue when finished. The hardware checks the content of the message queue and starts decoding the incoming data. The hardware processes the data read from the message queue and the processed data is then written back into the message queue for use by the software. The hardware raises an interrupt signal to the CPU when reaching the End tag. Speed differences between hardware and software can be compensated for by changing the depth of the queue.

摘要翻译： CPU（软件）和硬件之间的强制锁定步骤操作通过卸载CPU来监视硬件直到完成任务来消除。 这通过提供一个数据/控制消息队列来完成，CPU写入组合的数据/控制消息，并在结束时将一个End标签放入队列。 硬件检查消息队列的内容，并开始对传入的数据进行解码。 硬件处理从消息队列读取的数据，然后处理的数据被写回到消息队列中供软件使用。 当达到End标签时，硬件会向CPU提供中断信号给CPU。 可以通过改变队列的深度来补偿硬件和软件之间的速度差异。

公开(公告)号：US20070130394A1

公开(公告)日：2007-06-07

申请号：US11282531

申请日：2005-11-18

申请人： Lincheng Wang ,  Ching-Han Tsai ,  Cheng-Lun Chang ,  Uma Durvasula ,  Jau-Wen Ren

发明人： Lincheng Wang ,  Ching-Han Tsai ,  Cheng-Lun Chang ,  Uma Durvasula ,  Jau-Wen Ren

IPC分类号： G06F5/00

CPC分类号： G06F13/4234 ,  G06F2213/0038 ,  H04N21/443

摘要： A forced lock-step operation between a CPU (software) and the hardware is eliminated by unburdening the CPU from monitoring the hardware until it is finished with its task. This is done by providing a data/control message queue into which the CPU writes combined data/control messages and places an End tag into the queue when finished. The hardware checks the content of the message queue and starts decoding the incoming data. The hardware processes the data read from the message queue and the processed data is then written back into the message queue for use by the software. The hardware raises an interrupt signal to the CPU when reaching the End tag. Speed differences between hardware and software can be compensated for by changing the depth of the queue.

摘要翻译： CPU（软件）和硬件之间的强制锁定步骤操作通过卸载CPU来监视硬件直到完成任务来消除。 这通过提供一个数据/控制消息队列来完成，CPU写入组合的数据/控制消息，并在结束时将一个End标签放入队列。 硬件检查消息队列的内容，并开始对传入的数据进行解码。 硬件处理从消息队列读取的数据，然后处理的数据被写回到消息队列中供软件使用。 当达到End标签时，硬件会向CPU提供中断信号给CPU。 可以通过改变队列的深度来补偿硬件和软件之间的速度差异。

公开(公告)号：US07984211B2

公开(公告)日：2011-07-19

申请号：US12575446

申请日：2009-10-07

申请人： Lincheng Wang ,  Ching-Han Tsai ,  Cheng-Lun Chang ,  Uma Shankar Durvasula ,  Jau-Wen Ren

发明人： Lincheng Wang ,  Ching-Han Tsai ,  Cheng-Lun Chang ,  Uma Shankar Durvasula ,  Jau-Wen Ren

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： G06F13/4234 ,  G06F2213/0038 ,  H04N21/443

摘要： A forced lock-step operation between a CPU (software) and the hardware is eliminated by unburdening the CPU from monitoring the hardware until it is finished with its task. This is done by providing a data/control message queue into which the CPU writes combined data/control messages and places an End tag into the queue when finished. The hardware checks the content of the message queue and starts decoding the incoming data. The hardware processes the data read from the message queue and the processed data is then written back into the message queue for use by the software. The hardware raises an interrupt signal to the CPU when reaching the End tag. Speed differences between hardware and software can be compensated for by changing the depth of the queue.

摘要翻译： CPU（软件）和硬件之间的强制锁定步骤操作通过卸载CPU来监视硬件直到完成任务来消除。 这通过提供一个数据/控制消息队列来完成，CPU写入组合的数据/控制消息，并在结束时将一个End标签放入队列。 硬件检查消息队列的内容，并开始对传入的数据进行解码。 硬件处理从消息队列读取的数据，然后处理的数据被写回到消息队列中供软件使用。 当达到End标签时，硬件会向CPU提供中断信号给CPU。 可以通过改变队列的深度来补偿硬件和软件之间的速度差异。

公开(公告)号：US08950255B2

公开(公告)日：2015-02-10

申请号：US13463089

申请日：2012-05-03

申请人： Liang-Chi Chang ,  Cheng-Lun Chang ,  Ching-Jui Chen ,  Chao-Kai Cheng

发明人： Liang-Chi Chang ,  Cheng-Lun Chang ,  Ching-Jui Chen ,  Chao-Kai Cheng

IPC分类号： G01F23/22

CPC分类号： G01F23/22 ,  G01F23/248 ,  G01F23/268

摘要： A sensing device can detect material depth, liquid-level, and temperature. The sensing device has a probe, a control module, a volume sensing module, a thermal sensing module, an output module, and a power module. The probe has two material electrodes connected to the volume sensing module and a thermal electrode connected to the thermal sensing module. A rated voltage is applied at the material electrodes based on radio frequency admittance. A current deviation of the material electrodes is obtained by the volume sensing module, and calculated via the control module by material characteristics to obtain a correct storage amount of material. A temperature at each material depth is correctly detected by the thermal electrode. Steel cable is used as the material of the material electrodes of the probe to detect material depth or liquid level with high impact resistant ability.

摘要翻译： 感测装置可以检测材料深度，液位和温度。 感测装置具有探针，控制模块，体积感测模块，热感测模块，输出模块和功率模块。 探针具有连接到体积感测模块的两个材料电极和连接到热感测模块的热电极。 基于射频导纳在材料电极上施加额定电压。 通过体积检测模块获得材料电极的电流偏差，并通过控制模块通过材料特性计算，以获得正确的材料储存量。 每个材料深度的温度由热电极正确检测。 钢缆用作探头材料电极的材料，以检测具有高抗冲击能力的材料深度或液位。