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1.发明授权Method and apparatus to ensure functionality and timing robustness in SOI circuits 失效确保SOI电路的功能和时序稳健性的方法和装置公开(公告)号：US06608785B2
公开(公告)日：2003-08-19
申请号：US10041231
申请日：2002-01-07
IPC分类号： G11K700
CPC分类号： G11C29/028 , G11C29/50 , G11C29/50012 , G11C2029/5002
摘要： Methods and apparatus are provided to ensure functionality and timing robustness in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits. A select signal for the SOI CMOS circuit is received. A floating body charge monitoring circuit is coupled to the SOI CMOS circuit for monitoring excess body charges in at least one predefined SOI device and providing an output control signal. A select signal adjusting circuit is coupled to the floating body charge monitoring circuit receiving the output control signal and the select signal and providing a conditionally adjusted select signal responsive to the output control signal of the floating body charge monitor circuit. The conditionally adjusted select signal is applied to the SOI CMOS circuit. The conditionally adjusted select signal provided by the select signal adjusting circuit responsive to the output control signal of the floating body charge monitor circuit includes a predefined delay at the trailing edge of the select signal extending the select signal pulse width. The conditionally adjusted select signal includes a shortened select signal pulse having a predefined delay at the rising edge of the select signal. The conditionally adjusted select signal includes a substantially unchanged select signal pulse width with a predefined delay of the rising edge of the select signal.
摘要翻译： 提供了用于确保绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）电路中的功能和时序稳健性的方法和装置。 接收SOI CMOS电路的选择信号。 浮体电荷监测电路耦合到SOI CMOS电路，用于监测至少一个预定义SOI器件中的多余体电荷并提供输出控制信号。 选择信号调节电路耦合到接收输出控制信号和选择信号的浮动体电荷监视电路，并响应于浮动体电荷监视电路的输出控制信号提供有条件调节的选择信号。 有条件调整的选择信号被施加到SOI CMOS电路。 响应于浮动体电荷监视电路的输出控制信号，由选择信号调整电路提供的有条件调整的选择信号包括延伸选择信号脉冲宽度的选择信号的后沿处的预定延迟。 条件调整的选择信号包括在选择信号的上升沿具有预定延迟的缩短的选择信号脉冲。 条件调整的选择信号包括基本上不变的选择信号脉冲宽度，其中选择信号的上升沿具有预定义的延迟。
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2.发明授权Tri-state dynamic body charge modulation for sensing devices in SOI RAM applications 失效用于SOI RAM应用中感测器件的三态动态电荷调制公开(公告)号：US06373281B1
公开(公告)日：2002-04-16
申请号：US09767218
申请日：2001-01-22
IPC分类号： H03K1900
CPC分类号： G11C7/065
摘要： A method and apparatus are provided for tri-state dynamic body charge modulation for sensing devices in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) applications. A sense amplifier includes a silicon-on-insulator (SOI) field effect transistor. A tri-state body charge modulation circuit is coupled to a body of the silicon-on-insulator (SOI) field effect transistor. The body charge modulation circuit provides a high body bias preparatory state; a floating body state and a low body bias stand-by state enabling high performance operation, good matching characteristics, and low stand-by leakage suitable for low-power applications. The tri-state body charge modulation circuit includes a P-channel field effect transistor (PFET) and an N-channel field effect transistor (NFET) connected between a high voltage potential and ground. The junction of the series connected PFET and NFET is coupled to the SOI FET body for providing a charging path to a high power supply voltage rail and a discharging path to ground and a high impedance state.
摘要翻译： 提供了一种用于感测绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）应用中的器件的三态动态电荷调制的方法和装置。 读出放大器包括绝缘体上硅（SOI）场效应晶体管。 三态体电荷调制电路耦合到绝缘体上硅（SOI）场效应晶体管的主体。 身体电荷调制电路提供高体偏置准备状态; 浮体状态和低体态偏置待机状态，可实现高性能运行，良好的匹配特性，适用于低功率应用的低待机泄漏。 三态体电荷调制电路包括连接在高压电位和地之间的P沟道场效应晶体管（PFET）和N沟道场效应晶体管（NFET）。 串联连接的PFET和NFET的结连接到SOI FET体，用于提供到高电源电压轨的充电路径和到地的放电路径和高阻抗状态。
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3.发明申请Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices 有权使用非对称双栅极器件中二极管电压的独立控制改变电源电压或参考电压的方法和装置公开(公告)号：US20090302929A1
公开(公告)日：2009-12-10
申请号：US12511658
申请日：2009-07-29
IPC分类号： H03K3/01
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译： 提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。 提供由电源电压和参考电压中的一个或多个控制的集成电路。 集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。 独立控制可以包括例如背栅偏置。 独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。
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公开(公告)号：US20090303778A1
公开(公告)日：2009-12-10
申请号：US12511666
申请日：2009-07-29
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
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公开(公告)号：US06448830B1
公开(公告)日：2002-09-10
申请号：US10007854
申请日：2001-11-05
IPC分类号： H03K3037
CPC分类号： H03K3/3565
摘要： A tri-state Schmitt trigger inverting device having multiple tri-state controller switching devices between a conventional voltage mode Schmitt trigger its voltage supply rails. When an enabling signal to the tri-state controller switching devices is set to a first level, the tri-state Schmitt trigger functions as a standard logic inverter. When a complementary enabling signal is received at the tri-state controller switching devices, the connections to the high voltage rail and low voltage rail of the tri-state Schmitt trigger are turned off, and the output of the tri-state Schmitt trigger is a high impedance. Thus, the device is a single stage tri-state Schmitt inverter having optimal hysteresis characteristics with minimal power consumption.
摘要翻译： 在常规电压模式施密特触发其电压供应轨之间的具有多个三态控制器开关装置的三态施密特触发器反相装置。 当三态控制器开关器件的使能信号被设置为第一电平时，三态施密特触发器用作标准逻辑反相器。 当在三态控制器开关器件处接收到补充使能信号时，三态施密特触发器的与高电压轨和低电压轨的连接被关闭，并且三态施密特触发器的输出为 高阻抗。 因此，器件是具有最小功耗的最佳滞后特性的单级三态施密特逆变器。
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6.发明授权SOI CMOS sense amplifier with enhanced matching characteristics and sense point tolerance 失效SOI CMOS读出放大器具有增强的匹配特性和感测点容差公开(公告)号：US06222394B1
公开(公告)日：2001-04-24
申请号：US09498387
申请日：2000-02-03
IPC分类号： H03F345
CPC分类号： G11C7/065
摘要： A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) sense amplifier is provided with improved matching characteristics and sense point tolerance under no penalty of performance degradation. The sense amplifier includes a silicon-on-insulator (SOI) field effect transistor. A flooding field effect transistor is coupled to a body of the silicon-on-insulator (SOI) field effect transistor. The flooding field effect transistor is activated before the sense amplifier is set. The flooding field effect transistor has an opposite polarity of the silicon-on-insulator (SOI) field effect transistor. The flooding field effect transistor provides a charging path to a voltage supply rail. A pair of flooding field effect transistors serve as charging to voltage supply rail elements for silicon-on-insulator (SOI) field effect transistors on each side of complementary bitline structures of the sense amplifier. The flooding field effect transistor is substantially smaller than the silicon-on-insulator (SOI) field effect transistor.
摘要翻译： 绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）读出放大器具有改进的匹配特性和感测点容差，而不会降低性能。 读出放大器包括绝缘体上硅（SOI）场效应晶体管。 溢流场效应晶体管耦合到绝缘体上硅（SOI）场效应晶体管的主体。 溢流场效应晶体管在读出放大器设置之前被激活。 溢流场效应晶体管具有与绝缘体上硅（SOI）场效应晶体管相反的极性。 溢流场效应晶体管提供到电压供应轨的充电路径。 一对溢流场效应晶体管用作对读出放大器的互补位线结构的每一侧上的绝缘体上硅（SOI）场效应晶体管的电压供应轨元件的充电。 溢流场效应晶体管显着小于绝缘体上硅（SOI）场效应晶体管。
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7.发明授权Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices 有权使用不对称双栅极器件中二极管电压的独立控制来改变电源电压或参考电压的方法和装置公开(公告)号：US09076509B2
公开(公告)日：2015-07-07
申请号：US12511666
申请日：2009-07-29
IPC分类号： G11C11/00 , G11C5/14 , G11C11/412 , G11C11/417
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译： 提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。 提供由电源电压和参考电压中的一个或多个控制的集成电路。 集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。 独立控制可以包括例如背栅偏置。 独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。
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公开(公告)号：US06441663B1
公开(公告)日：2002-08-27
申请号：US09704436
申请日：2000-11-02
IPC分类号： H03K3037
CPC分类号： H03K3/3565
摘要： A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) Schmitt trigger circuit with controllable hysteresis and a method are provided for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications. A SOI CMOS Schmitt trigger circuit with controllable hysteresis includes a stack of a plurality of field effect transistors (FETs) connected in series between a voltage supply and ground. An input is applied to a gate of each of the stack of the plurality of field effect transistors (FETs). The stack of the plurality of field effect transistors (FETs) provides an output at a junction of a predetermined pair of the plurality of field effect transistors (FETs). At least one feedback field effect transistor (FET) has a source coupled a junction of a predefined pair of the stack of field effect transistors (FETs) and has a gate coupled to the output. A FET body of each of the stack of the plurality of field effect transistors (FETs) is connected to a voltage supply rail. The stack of the plurality of field effect transistors (FETs) includes a plurality of P-channel field effect transistors (PFETs) and a plurality of N-channel field effect transistors (NFETs). The FET body of each of the plurality of P-channel field effect transistors (PFETs) is connected to a positive voltage supply rail and the FET body of each of the plurality of N-channel field effect transistors (NFETs) is connected to a voltage supply ground rail. The FET body of a P-channel feedback field effect transistor (PFET) is connected to one of a positive voltage supply rail, the gate or the source of the feedback PFET. The FET body of a N-channel feedback field effect transistor (NFET) is connected to one of a voltage supply ground rail, the gate or the source of the feedback NFET. A successive switching threshold adjustment technique is provided. Additional successive switching threshold adjustment is achieved by successive tapping of NFET or PFET feedback devices for the V+ or the V− trigger edges, respectively. With this arrangement, higher V+ and lower V− are realized without using excessively wide NFET or PFET feedback devices.
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9.发明授权Method and apparatus for improving device matching and switching point tolerance in silicon-on-insulator cross-coupled circuits 失效用于提高绝缘体上交叉耦合电路中的器件匹配和开关点容差的方法和装置公开(公告)号：US06252429B1
公开(公告)日：2001-06-26
申请号：US09317733
申请日：1999-05-24
IPC分类号： G11C706
CPC分类号： G11C7/065
摘要： An apparatus for improving device matching and switching point tolerance in a silicon-on-insulator cross-coupled circuit is disclosed. The silicon-on-insulator circuit includes first and second sets of transistors, first and second rails, and first and second discharge transistors. The first set of transistors is cross-coupled with the second set of transistors. The first rail is connected to each gate of the transistors in the first set, and the second rail is connected to each gate of the transistors in the second set. The body of at least one transistor within the first set of transistors is connected to the first discharge transistor having the same channel type as the connected transistor. The body of at least one transistor within the second set of transistors is connected to the second discharge transistor having the same channel type as the connected transistor. The gate of the first discharge transistor is controlled by the second rail, and the gate of the second discharge transistor is controlled by the first rail.
摘要翻译： 公开了一种用于提高绝缘体上硅交叉耦合电路中的器件匹配和开关点公差的装置。 绝缘体上硅电路包括第一和第二组晶体管，第一和第二导轨以及第一和第二放电晶体管。 第一组晶体管与第二组晶体管交叉耦合。 第一轨道连接到第一组中的晶体管的每个栅极，并且第二轨道连接到第二组中的晶体管的每个栅极。 第一组晶体管内的至少一个晶体管的主体连接到具有与连接的晶体管相同的沟道类型的第一放电晶体管。 第二组晶体管内的至少一个晶体管的主体连接到具有与连接的晶体管相同的沟道类型的第二放电晶体管。 第一放电晶体管的栅极由第二导轨控制，第二放电晶体管的栅极由第一导轨控制。
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10.发明授权High-density logic techniques with reduced-stack multi-gate field effect transistors 有权具有减少堆叠多栅极场效应晶体管的高密度逻辑技术公开(公告)号：US07382162B2
公开(公告)日：2008-06-03
申请号：US11181954
申请日：2005-07-14
IPC分类号： H03K19/20 , H03K19/094
CPC分类号： H03K19/0948 , H01L29/78648
摘要： Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.
摘要翻译： 提供了在由逻辑门形成的逻辑电路中采用多栅极场效应晶体管（FETS）的技术。 只有当两个晶体管栅极有效时才导通的双栅极晶体管可以用于减少逻辑门串联或“堆叠”部分所需的器件数量。 可以减小电路面积，提高性能。
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