公开(公告)号：US5176197A

公开(公告)日：1993-01-05

申请号：US771808

申请日：1991-10-08

申请人： Chiyokatsu Hamaguchi ,  Tomoharu Shimokasa ,  Kazumi Daitoku ,  Fujiya Nogami ,  Kazuya Kudo ,  Kazumi Seki

发明人： Chiyokatsu Hamaguchi ,  Tomoharu Shimokasa ,  Kazumi Daitoku ,  Fujiya Nogami ,  Kazuya Kudo ,  Kazumi Seki

IPC分类号： B22D11/04 ,  B22D11/059

CPC分类号： B22D11/0401 ,  B22D11/059

摘要： A continuous caster mold has a water-cooled inner wall of copper or a copper alloy that is thoroughly covered with pieces of ceramics. A continuous casting process, which uses a mold whose inner wall of copper or a copper alloy is lined with ceramics having resistance to wear, heat and thermal shock, heat conductivity and lubricating property, with the thickness of the ceramics lining varied either stepwise or continuously in the casting direction. The molten metal, which progressively solidifies as its heat is extracted, is withdrawn by taking advantage of the solid lubrication provided by the ceramics lining. The thickness of the lining is varied to prevent the formation of air gaps between the surface of the lining and the solidifying shell and cool the steel being cast according to the desired pattern, and/or to start solidification of the molten metal below the molten metal surface level.

摘要翻译： 连续铸造模具具有铜或铜合金的水冷内壁，被陶瓷件完全覆盖。 一种连续铸造工艺，其使用铜或铜合金的内壁衬有具有耐磨损，热和热冲击，导热性和润滑性能的陶瓷的模具，其中陶瓷衬里的厚度逐步或连续地变化 在铸造方向。 通过利用由陶瓷衬里提供的固体润滑剂的方式，将提取出的热量逐渐凝固的熔融金属抽出。 衬里的厚度是变化的，以防止在衬里表面和凝固壳之间形成气隙，并根据期望的图案冷却正在铸造的钢，和/或开始熔融金属下方的凝固 表面水平

公开(公告)号：US07698613B2

公开(公告)日：2010-04-13

申请号：US11683954

申请日：2007-03-08

申请人： Kazuya Kudo

发明人： Kazuya Kudo

IPC分类号： G01R31/28

CPC分类号： G01R31/318594 ,  G01R31/318552

摘要： Disclosed is a circuit in which for conducting the scan path test, test clock terminals are provided in a number smaller than that of user clock domains, and a test clock control circuits on respective test clock lines to control whether the pulses of the test clock are propagated or blocked.

摘要翻译： 公开了一种用于进行扫描路径测试的电路，其测试时钟端子的数量小于用户时钟域的数量，以及在各个测试时钟线路上的测试时钟控制电路，以控制测试时钟的脉冲是否为 传播或阻止

公开(公告)号：US06370663B1

公开(公告)日：2002-04-09

申请号：US09225434

申请日：1999-01-05

申请人： Kazuya Kudo

发明人： Kazuya Kudo

IPC分类号： G01R3128

CPC分类号： G01R31/318547

摘要： A semiconductor integrated circuit comprises a first circuit block constituting an input circuit, a second circuit block constituted of a predetermined function block, a third circuit block constituting an output circuit. The first, second and third circuit blocks are cascade-connected in a normal operation. A testing additional circuit for performing a function test for the second circuit block, is provided only at an input side of the second circuit block, and the second circuit block is connected directly to the third circuit block through only interconnections with neither a logic gate nor a multiplexer.

摘要翻译： 半导体集成电路包括构成输入电路的第一电路块，由预定功能块构成的第二电路块，构成输出电路的第三电路块。 第一，第二和第三电路块在正常操作中级联连接。 仅在第二电路块的输入侧提供用于执行第二电路块的功能测试的测试附加电路，并且第二电路块仅通过逻辑门或逻辑门的互连直接连接到第三电路块 多路复用器