公开(公告)号：US08595658B2

公开(公告)日：2013-11-26

申请号：US12147200

申请日：2008-06-26

申请人： Chooi Pei Lim ,  Joo Ming Too ,  Yew Fatt Kok ,  Kar Keng Chua

发明人： Chooi Pei Lim ,  Joo Ming Too ,  Yew Fatt Kok ,  Kar Keng Chua

IPC分类号： G06F17/50

CPC分类号： H03K19/1774 ,  G06F1/10

摘要： Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

公开(公告)号：US20080258772A1

公开(公告)日：2008-10-23

申请号：US12147200

申请日：2008-06-26

申请人： Chooi Pei Lim ,  Joo Ming Too ,  Yew Fatt (Edwin) Kok ,  Kar Keng Chua

发明人： Chooi Pei Lim ,  Joo Ming Too ,  Yew Fatt (Edwin) Kok ,  Kar Keng Chua

IPC分类号： H03K19/096

CPC分类号： H03K19/1774 ,  G06F1/10

摘要： Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

摘要翻译： 用于结构化ASIC器件的时钟分配电路包括确定性部分和可配置部分。 确定性部分采用预定布置的导体段和缓冲器，用于将时钟信号分配到设备上的多个预定位置。 从每个预定位置，时钟分配电路的相关联的可配置部分将时钟信号分配到在从该预定位置服务的结构化ASIC的预定区域中需要该时钟信号的任何时钟利用电路。

公开(公告)号：US07404169B2

公开(公告)日：2008-07-22

申请号：US11141867

申请日：2005-05-31

申请人： Chooi Pei Lim ,  Joo Ming Too ,  Yew Fatt (Edwin) Kok ,  Kar Keng Chua

发明人： Chooi Pei Lim ,  Joo Ming Too ,  Yew Fatt (Edwin) Kok ,  Kar Keng Chua

IPC分类号： G06F17/50

CPC分类号： H03K19/1774 ,  G06F1/10

摘要： Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

摘要翻译： 用于结构化ASIC器件的时钟分配电路包括确定性部分和可配置部分。 确定性部分采用预定布置的导体段和缓冲器，用于将时钟信号分配到设备上的多个预定位置。 从每个预定位置，时钟分配电路的相关联的可配置部分将时钟信号分配到在从该预定位置服务的结构化ASIC的预定区域中需要该时钟信号的任何时钟利用电路。

公开(公告)号：US07675336B1

公开(公告)日：2010-03-09

申请号：US11016394

申请日：2004-12-17

申请人： Kok Yoong Foo ,  Tze Haw Liew ,  Joo Ming Too

发明人： Kok Yoong Foo ,  Tze Haw Liew ,  Joo Ming Too

IPC分类号： H03K3/017 ,  H03K5/04 ,  H03K7/08

CPC分类号： H03K5/1565

摘要： Circuits, methods, and apparatus that provide the improvement or recovery of a duty cycle of a clock signal. One embodiment of the present invention receives a clock signal that may have a degraded duty cycle. The frequency of the clock signal is divided by two. The frequency-divided signal is delayed in order to generate two signals that are phase shifted from one another by 90 degrees. These signals are then exclusive-ORed together to generate a recovered clock. A control loop is provided to adjust the phase shift between the signals to be approximately 90 degrees.

摘要翻译： 提供时钟信号的占空比的改进或恢复的电路，方法和装置。 本发明的一个实施例接收可能具有降低的占空比的时钟信号。 时钟信号的频率除以2。 分频信号被延迟以产生彼此相移90度的两个信号。 这些信号然后被异或在一起以产生恢复的时钟。 提供控制回路以将信号之间的相移调整为大约90度。