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13 条记录 (耗时 0.013 秒)

    Multi-layer distributed network
    1.
    发明授权
    Multi-layer distributed network 有权
    多层分布式网络

    公开(公告)号：US08683405B2

    公开(公告)日：2014-03-25

    申请号：US13418958

    申请日：2012-03-13

    申请人： Keong Hong Oh ,  Yee Liang Tan ,  Siang Poh Lob ,  Chooi Pei Lim

    发明人： Keong Hong Oh ,  Yee Liang Tan ,  Siang Poh Lob ,  Chooi Pei Lim

    IPC分类号： G06F17/50

    CPC分类号： G06F13/40 ,  G06F17/505 ,  G06F17/5054 ,  G06F2217/14 ,  G06F2217/62 ,  G06F2217/84

    摘要： Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.

    摘要翻译： 公开了用于在集成电路中分配信号的装置和过程。 在集成电路上用于测试集成电路的基层与定制层一起使用的实施例包括在基础层上具有结构化网络。 定制层将网络连接到集成电路上的逻辑元件。 网络可以均匀分布在集成电路的基础层上。 网络的均匀分布可能减少测试信号的偏差。 缓冲区也沿着结构化网络放置。 可以放置缓冲器以确保确定性的测试信号分布。 基层中的未使用的缓冲区可能被关闭以​​减少电流泄漏。

    Clock signal networks for structured ASIC devices
    2.
    发明授权
    Clock signal networks for structured ASIC devices 失效

    公开(公告)号：US08595658B2

    公开(公告)日：2013-11-26

    申请号：US12147200

    申请日：2008-06-26

    申请人： Chooi Pei Lim ,  Joo Ming Too ,  Yew Fatt Kok ,  Kar Keng Chua

    发明人： Chooi Pei Lim ,  Joo Ming Too ,  Yew Fatt Kok ,  Kar Keng Chua

    IPC分类号： G06F17/50

    CPC分类号： H03K19/1774 ,  G06F1/10

    摘要： Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

    Stacked integrated circuit with redundancy in die-to-die interconnects
    5.
    发明授权
    Stacked integrated circuit with redundancy in die-to-die interconnects 有权
    堆叠式集成电路在管芯到芯片互连中具有冗余

    公开(公告)号：US09236864B1

    公开(公告)日：2016-01-12

    申请号：US13352212

    申请日：2012-01-17

    申请人： Siang Poh Loh ,  Chooi Pei Lim

    发明人： Siang Poh Loh ,  Chooi Pei Lim

    IPC分类号： H01L23/02 ,  H03K19/003 ,  H01L23/538

    CPC分类号： H03K19/003 ,  G11C29/702 ,  H01L23/538 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H03K19/00315

    摘要： An integrated circuit (IC) is provided where the IC includes a first die, a second die stacked above the first die, and a plurality of die-to-die interconnects coupling the first die to the second die, where the plurality of die-to-die interconnects includes at least one redundancy die-to-die interconnect. In one implementation, the plurality of die-to-die interconnects includes a plurality of pre-designated die-to-die interconnects, where if a pre-designated die-to-die interconnect of the plurality of pre-designated die-to-die interconnects is defective, then signals intended for transmission via the pre-designated die-to-die interconnect are instead transmitted via the at least one redundancy die-to-die interconnect.

    摘要翻译： 提供集成电路（IC），其中IC包括第一管芯，堆叠在第一管芯上方的第二管芯，以及将第一管芯耦合到第二管芯的多个管芯到管芯互连，其中多个管芯 - 芯片间互连包括至少一个冗余裸片到芯片互连。 在一个实现中，多个管芯到管芯互连包括多个预先指定的管芯到管芯互连，其中如果多个预先指定的管芯到管芯互连的预先指定的管芯到管芯互连， 芯片互连是有缺陷的，则经由预先指定的管芯到芯片互连的旨在传输的信号代替地通过至少一个冗余管芯到芯片互连传输。

    Mask set for fabricating integrated circuits and method of fabricating integrated circuits
    6.
    发明授权
    Mask set for fabricating integrated circuits and method of fabricating integrated circuits 有权
    用于制造集成电路的掩模组和制造集成电路的方法

    公开(公告)号：US08758961B1

    公开(公告)日：2014-06-24

    申请号：US13246761

    申请日：2011-09-27

    申请人： Jordan Plofsky ,  Chooi Pei Lim ,  Danny Biran ,  Francis Man-Chit Chow

    发明人： Jordan Plofsky ,  Chooi Pei Lim ,  Danny Biran ,  Francis Man-Chit Chow

    IPC分类号： G03F9/00

    CPC分类号： H01L21/283 ,  G03F1/00 ,  G03F1/50 ,  H01L21/78 ,  H01L23/544 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A mask set is described. In one implementation, the mask set includes: a first layer mask including a plurality of first tiles of a first tile size; and a second layer mask including a plurality of second tiles of a second tile size, where the second tile size is different from the first tile size. Also, a method of fabricating a plurality of integrated circuits (ICs) is described. In one implementation, the method includes: using a first layer mask having a first tile size to fabricate a first layer of a first IC of the plurality of ICs and a first layer of a second IC of the plurality of ICs; and using a second layer mask having a second tile size to fabricate a second layer of the first IC, where the second tile size is different from the first tile size.

    摘要翻译： 描述掩模集。 在一个实现中，掩模集包括：第一层掩模，其包括具有第一块尺寸的多个第一瓦片; 以及第二层掩模，其包括第二块尺寸的多个第二块，其中第二块尺寸不同于第一块尺寸。 此外，描述了制造多个集成电路（IC）的方法。 在一个实现中，该方法包括：使用具有第一块尺寸的第一层掩模来制造多个IC中的第一IC的第一层和多个IC中的第二IC的第一层; 以及使用具有第二块尺寸的第二层掩模来制造所述第一IC的第二层，其中所述第二块尺寸不同于所述第一块尺寸。

    Multi-layer distributed network
    7.
    发明授权
    Multi-layer distributed network 有权
    多层分布式网络

    公开(公告)号：US08166429B1

    公开(公告)日：2012-04-24

    申请号：US12253910

    申请日：2008-10-17

    申请人： Keong Hong Oh ,  Yee Liang Tan ,  Siang Poh Loh ,  Chooi Pei Lim

    发明人： Keong Hong Oh ,  Yee Liang Tan ,  Siang Poh Loh ,  Chooi Pei Lim

    IPC分类号： G06F17/50

    CPC分类号： G06F13/40 ,  G06F17/505 ,  G06F17/5054 ,  G06F2217/14 ,  G06F2217/62 ,  G06F2217/84

    摘要： Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base layer. The custom layer connects the network to logic elements on the integrated circuit. The network may be evenly distributed across the base layer of the integrated circuit. Even distribution of the network may reduce skew of the test signals. Buffers are also placed along the structured network. The buffers may be placed to ensure a deterministic test signals distribution. Unused buffers in the base layer may be tied off to reduce current leakage.

    摘要翻译： 公开了用于在集成电路中分配信号的装置和过程。 在集成电路上用于测试集成电路的基层与定制层一起使用的实施例包括在基础层上具有结构化网络。 定制层将网络连接到集成电路上的逻辑元件。 网络可以均匀分布在集成电路的基础层上。 网络的均匀分布可能减少测试信号的偏差。 缓冲区也沿着结构化网络放置。 可以放置缓冲器以确保确定性的测试信号分布。 基层中的未使用的缓冲区可能被关闭以​​减少电流泄漏。

    Periphery clock signal distribution circuitry for structured ASIC devices
    8.
    发明授权
    Periphery clock signal distribution circuitry for structured ASIC devices 失效
    用于结构化ASIC器件的周边时钟信号分配电路

    公开(公告)号：US07622952B1

    公开(公告)日：2009-11-24

    申请号：US12156090

    申请日：2008-05-28

    申请人： Chooi Pei Lim ,  Siang Poh Loh ,  Hong Ming Siew

    发明人： Chooi Pei Lim ,  Siang Poh Loh ,  Hong Ming Siew

    IPC分类号： H03K19/177 ,  H01L25/00

    CPC分类号： H03K19/1774 ,  G06F1/10 ,  H03K19/17744

    摘要： A structured ASIC device includes highly flexible clock signal routing to peripheral IO circuitry of the device. A plurality of peripheral IO circuits are divided into subpluralities of adjacent ones of those circuits. Each subplurality has associated clock signal routing that is mask-programmable to supply any of a plurality of clock signals to any of the IO circuits in the subplurality. Core circuitry of the structured ASIC includes clock signal distribution circuitry, and that distribution circuitry can supply (via buffers associated with each subplurality) the same plurality of clock signals to the routing circuitry associated with all of the subpluralities.

    摘要翻译： 结构化ASIC器件包括高度灵活的时钟信号路由到设备的外围IO电路。 多个外围IO电路被划分成这些电路中的相邻电路的子部件。 每个子层具有可屏蔽可编程的相关联的时钟信号路由，以将多个时钟信号中的任何一个提供给子空间中的任何IO电路。 结构化ASIC的核心电路包括时钟信号分配电路，并且该分配电路可以将相同的多个时钟信号（通过与每个子模式相关联的缓冲器）提供给与所有子实体相关联的路由电路。

    CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES
    9.
    发明申请
    CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES 失效
    用于结构化ASIC器件的时钟信号网络

    公开(公告)号：US20080258772A1

    公开(公告)日：2008-10-23

    申请号：US12147200

    申请日：2008-06-26

    申请人： Chooi Pei Lim ,  Joo Ming Too ,  Yew Fatt (Edwin) Kok ,  Kar Keng Chua

    发明人： Chooi Pei Lim ,  Joo Ming Too ,  Yew Fatt (Edwin) Kok ,  Kar Keng Chua

    IPC分类号： H03K19/096

    CPC分类号： H03K19/1774 ,  G06F1/10

    摘要： Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

    摘要翻译： 用于结构化ASIC器件的时钟分配电路包括确定性部分和可配置部分。 确定性部分采用预定布置的导体段和缓冲器，用于将时钟信号分配到设备上的多个预定位置。 从每个预定位置，时钟分配电路的相关联的可配置部分将时钟信号分配到在从该预定位置服务的结构化ASIC的预定区域中需要该时钟信号的任何时钟利用电路。