公开(公告)号：US20150178319A1

公开(公告)日：2015-06-25

申请号：US13305352

申请日：2011-11-28

申请人： Chris CO ,  Jayant Kolhe

发明人： Chris CO ,  Jayant Kolhe

IPC分类号： G06F17/30

CPC分类号： G06F16/5866 ,  G06F16/29

摘要： A computer-implemented method, system and computer-readable medium for suggesting a date to display a historical image, is provided. A plurality of tiles corresponding to a geographic area are identified. Some or all of the geographic area can be displayed to a user. For each tile, a list of dates is identified, each date in the list associated with a historical image geolocated at a geolocation of each tile on a particular date. From the list of dates associated with each tile, an oldest date is identified. The oldest date from each list of dates associated with each tile is compiled into a suggested date list. From the suggested date list, a date is selected as the suggested date, that accounts for the age of available historical images and the availability of historical images having the suggested date within the image displayed to the user.

摘要翻译： 提供了一种用于建议显示历史图像的日期的计算机实现的方法，系统和计算机可读介质。 识别与地理区域对应的多个瓦片。 可以向用户显示部分或全部地理区域。 对于每个瓦片，识别日期的列表，列表中的每个日期与在特定日期的每个瓦片的地理定位处地理定位的历史图像相关联。 从与每个图块相关联的日期列表中，识别最早的日期。 从与每个图块相关联的每个日期列表中的最早日期被编译成建议的日期列表。 从建议的日期列表中，选择一个日期作为建议日期，其中说明可用的历史图像的年龄，以及在向用户显示的图像中具有建议日期的历史图像的可用性。

公开(公告)号：US20060225061A1

公开(公告)日：2006-10-05

申请号：US11096404

申请日：2005-03-31

申请人： Michael Ludwig ,  Jayant Kolhe ,  Robert Glanville ,  Geoffrey Berry ,  Boris Beylin ,  Michael Bunnell

发明人： Michael Ludwig ,  Jayant Kolhe ,  Robert Glanville ,  Geoffrey Berry ,  Boris Beylin ,  Michael Bunnell

IPC分类号： G06F9/45

CPC分类号： G06F8/441 ,  G06T15/005

摘要： A method and apparatus for optimizing register allocation during scheduling and execution of program code in a hardware environment. The program code can be compiled to optimize execution given predetermined hardware constraints. The hardware constraints can include the number of register read and write operations that can be performed in a given processor pass. The optimizer can initially schedule the program using virtual registers and a goal of minimizing the amount of active registers at any time. The optimizer reschedules the program to assign the virtual registers to actual physical registers in a manner that minimizes the number of processor passes used to execute the program.

摘要翻译： 一种用于在硬件环境中调度和执行程序代码期间优化寄存器分配的方法和装置。 可以编译程序代码，以在给定预定的硬件约束条件下优化执行。 硬件约束可以包括可以在给定处理器通行证中执行的寄存器读和写操作的数量。 优化器最初可以使用虚拟寄存器来调度程序，并且可以在任何时候最小化活动寄存器的数量。 优化器重新调度程序，以最小化用于执行程序的处理器通过次数的方式将虚拟寄存器分配给实际物理寄存器。

公开(公告)号：US08281294B1

公开(公告)日：2012-10-02

申请号：US11938755

申请日：2007-11-12

申请人： Julius Vanderspek ,  Nicholas Patrick Wilt ,  Jayant Kolhe ,  Ian A. Buck ,  Bastiaan Aarts

发明人： Julius Vanderspek ,  Nicholas Patrick Wilt ,  Jayant Kolhe ,  Ian A. Buck ,  Bastiaan Aarts

IPC分类号： G06F9/45

CPC分类号： G06F9/44547 ,  G06F8/447

摘要： One embodiment of the present invention sets forth a technique for representing and managing a multi-architecture co-processor application program. Source code for co-processor functions is compiled in two stages. The first stage incorporates a majority of the computationally intensive processing steps associated with co-processor code compilation. The first stage generates virtual assembly code from the source code. The second stage generates co-processor machine code from the virtual assembly. Both the virtual assembly and co-processor machine code may be included within the co-processor enabled application program. A co-processor driver uses a description of the currently available co-processor to select between virtual assembly and co-processor machine code. If the virtual assembly code is selected, then the co-processor driver compiles the virtual assembly into machine code for the current co-processor.

摘要翻译： 本发明的一个实施例提出了一种用于表示和管理多架构协处理器应用程序的技术。 协处理器功能的源代码分两个阶段编译。 第一阶段包含与协处理器代码编译相关联的大部分计算密集型处理步骤。 第一阶段从源代码生成虚拟汇编代码。 第二阶段从虚拟程序集中生成协处理器机器代码。 虚拟装配和协处理器机器码都可以包括在支持协处理器的应用程序中。 协处理器驱动程序使用当前可用的协处理器的描述来在虚拟装配和协处理器机器代码之间进行选择。 如果选择了虚拟汇编代码，则协处理器驱动程序将虚拟程序集编译为当前协处理器的机器代码。

公开(公告)号：US08276132B1

公开(公告)日：2012-09-25

申请号：US11938747

申请日：2007-11-12

申请人： Julius Vanderspek ,  Nicholas Patrick Wilt ,  Jayant Kolhe ,  Ian A. Buck ,  Bastiaan Aarts

发明人： Julius Vanderspek ,  Nicholas Patrick Wilt ,  Jayant Kolhe ,  Ian A. Buck ,  Bastiaan Aarts

IPC分类号： G06F9/45

CPC分类号： G06F8/36 ,  G06F8/30 ,  G06F9/45516

摘要： One embodiment of the present invention sets forth a technique for representing and managing a multi-architecture co-processor application program. Source code for co-processor functions is compiled in two stages. The first stage incorporates a majority of the computationally intensive processing steps associated with co-processor code compilation. The first stage generates virtual assembly code from the source code. The second stage generates co-processor machine code from the virtual assembly. Both the virtual assembly and co-processor machine code may be included within the co-processor enabled application program. A co-processor driver uses a description of the currently available co-processor to select between virtual assembly and co-processor machine code. If the virtual assembly code is selected, then the co-processor driver compiles the virtual assembly into machine code for the current co-processor.

公开(公告)号：US08347310B1

公开(公告)日：2013-01-01

申请号：US11938750

申请日：2007-11-12

申请人： Julius Vanderspek ,  Nicholas Patrick Wilt ,  Jayant Kolhe ,  Ian A. Buck ,  Bastiaan Aarts

发明人： Julius Vanderspek ,  Nicholas Patrick Wilt ,  Jayant Kolhe ,  Ian A. Buck ,  Bastiaan Aarts

IPC分类号： G06F3/00 ,  G06F9/44

CPC分类号： G06F8/447

摘要： One embodiment of the present invention sets forth a technique for representing and managing a multi-architecture co-processor application program. Source code for co-processor functions is compiled in two stages. The first stage incorporates a majority of the computationally intensive processing steps associated with co-processor code compilation. The first stage generates virtual assembly code from the source code. The second stage generates co-processor machine code from the virtual assembly. Both the virtual assembly and co-processor machine code may be included within the co-processor enabled application program. A co-processor driver uses a description of the currently available co-processor to select between virtual assembly and co-processor machine code. If the virtual assembly code is selected, then the co-processor driver compiles the virtual assembly into machine code for the current co-processor.

摘要翻译： 本发明的一个实施例提出了一种用于表示和管理多架构协处理器应用程序的技术。 协处理器功能的源代码分两个阶段编译。 第一阶段包含与协处理器代码编译相关联的大部分计算密集型处理步骤。 第一阶段从源代码生成虚拟汇编代码。 第二阶段从虚拟程序集中生成协处理器机器代码。 虚拟装配和协处理器机器码都可以包括在支持协处理器的应用程序中。 协处理器驱动程序使用当前可用的协处理器的描述来在虚拟装配和协处理器机器代码之间进行选择。 如果选择了虚拟汇编代码，则协处理器驱动程序将虚拟程序集编译为当前协处理器的机器代码。

公开(公告)号：US20070113223A1

公开(公告)日：2007-05-17

申请号：US11274602

申请日：2005-11-14

申请人： Michael Ludwig ,  Jayant Kolhe

发明人： Michael Ludwig ,  Jayant Kolhe

IPC分类号： G06F9/45

CPC分类号： G06F8/445

摘要： A list scheduler in a compiler can select from a plurality of alternative instruction sequences for one or more computation performed within an application. A scheduler can initially identify and track one or more computations for which multiple alternative instruction sequences exist. An available instruction list can be populated with the alternative instruction sequences. The list scheduler can access the available instruction list during scheduling of the application. The list scheduler can perform a cost analysis while scheduling the instructions by performing a look ahead. The list scheduler may select alternate instruction sequences for similar computations occurring in different portions of the application based on the cost benefit analysis.

摘要翻译： 编译器中的列表调度器可以从多个替代指令序列中选择一个或多个在应用程序内执行的计算。 调度器可以初始地识别并跟踪存在多个备选指令序列的一个或多个计算。 可以使用替代指令序列来填充可用的指令列表。 列表调度程序可以在应用程序调度期间访问可用的指令列表。 列表调度程序可以通过执行预览来调度指令来执行成本分析。 列表调度器可以基于成本效益分析来选择在应用的不同部分中发生的类似计算的替代指令序列。