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1.发明授权System and method for representing and managing a multi-architecure co-processor application program 有权用于表示和管理多架构协处理器应用程序的系统和方法公开(公告)号：US08347310B1
公开(公告)日：2013-01-01
申请号：US11938750
申请日：2007-11-12
CPC分类号： G06F8/447
摘要： One embodiment of the present invention sets forth a technique for representing and managing a multi-architecture co-processor application program. Source code for co-processor functions is compiled in two stages. The first stage incorporates a majority of the computationally intensive processing steps associated with co-processor code compilation. The first stage generates virtual assembly code from the source code. The second stage generates co-processor machine code from the virtual assembly. Both the virtual assembly and co-processor machine code may be included within the co-processor enabled application program. A co-processor driver uses a description of the currently available co-processor to select between virtual assembly and co-processor machine code. If the virtual assembly code is selected, then the co-processor driver compiles the virtual assembly into machine code for the current co-processor.
摘要翻译： 本发明的一个实施例提出了一种用于表示和管理多架构协处理器应用程序的技术。 协处理器功能的源代码分两个阶段编译。 第一阶段包含与协处理器代码编译相关联的大部分计算密集型处理步骤。 第一阶段从源代码生成虚拟汇编代码。 第二阶段从虚拟程序集中生成协处理器机器代码。 虚拟装配和协处理器机器码都可以包括在支持协处理器的应用程序中。 协处理器驱动程序使用当前可用的协处理器的描述来在虚拟装配和协处理器机器代码之间进行选择。 如果选择了虚拟汇编代码，则协处理器驱动程序将虚拟程序集编译为当前协处理器的机器代码。
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2.发明授权System and method for representing and managing a multi-architecture co-processor application program 有权用于表示和管理多架构协处理器应用程序的系统和方法公开(公告)号：US08281294B1
公开(公告)日：2012-10-02
申请号：US11938755
申请日：2007-11-12
IPC分类号： G06F9/45
CPC分类号： G06F9/44547 , G06F8/447
摘要： One embodiment of the present invention sets forth a technique for representing and managing a multi-architecture co-processor application program. Source code for co-processor functions is compiled in two stages. The first stage incorporates a majority of the computationally intensive processing steps associated with co-processor code compilation. The first stage generates virtual assembly code from the source code. The second stage generates co-processor machine code from the virtual assembly. Both the virtual assembly and co-processor machine code may be included within the co-processor enabled application program. A co-processor driver uses a description of the currently available co-processor to select between virtual assembly and co-processor machine code. If the virtual assembly code is selected, then the co-processor driver compiles the virtual assembly into machine code for the current co-processor.
摘要翻译： 本发明的一个实施例提出了一种用于表示和管理多架构协处理器应用程序的技术。 协处理器功能的源代码分两个阶段编译。 第一阶段包含与协处理器代码编译相关联的大部分计算密集型处理步骤。 第一阶段从源代码生成虚拟汇编代码。 第二阶段从虚拟程序集中生成协处理器机器代码。 虚拟装配和协处理器机器码都可以包括在支持协处理器的应用程序中。 协处理器驱动程序使用当前可用的协处理器的描述来在虚拟装配和协处理器机器代码之间进行选择。 如果选择了虚拟汇编代码，则协处理器驱动程序将虚拟程序集编译为当前协处理器的机器代码。
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公开(公告)号：US08276132B1
公开(公告)日：2012-09-25
申请号：US11938747
申请日：2007-11-12
IPC分类号： G06F9/45
CPC分类号： G06F8/36 , G06F8/30 , G06F9/45516
摘要： One embodiment of the present invention sets forth a technique for representing and managing a multi-architecture co-processor application program. Source code for co-processor functions is compiled in two stages. The first stage incorporates a majority of the computationally intensive processing steps associated with co-processor code compilation. The first stage generates virtual assembly code from the source code. The second stage generates co-processor machine code from the virtual assembly. Both the virtual assembly and co-processor machine code may be included within the co-processor enabled application program. A co-processor driver uses a description of the currently available co-processor to select between virtual assembly and co-processor machine code. If the virtual assembly code is selected, then the co-processor driver compiles the virtual assembly into machine code for the current co-processor.
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4.发明授权System and method for enabling interoperability between application programming interfaces 有权用于实现应用程序编程接口之间的互操作性的系统和方法公开(公告)号：US08402229B1
公开(公告)日：2013-03-19
申请号：US12031682
申请日：2008-02-14
IPC分类号： G06F13/16
CPC分类号： G09G5/001
摘要： One embodiment of the present invention sets forth a method for sharing graphics objects between a compute unified device architecture (CUDA) application programming interface (API) and a graphics API. The CUDA API includes calls used to alias graphics objects allocated by the graphics API and, subsequently, synchronize accesses to the graphics objects. When an application program emits a “register” call that targets a particular graphics object, the CUDA API ensures that the graphics object is in the device memory, and maps the graphics object into the CUDA address space. Subsequently, when the application program emits “map” and “unmap” calls, the CUDA API respectively enables and disables accesses to the graphics object through the CUDA API. Further, the CUDA API uses semaphores to synchronize accesses to the shared graphics object. Finally, when the application program emits an “unregister” call, the CUDA API configures the computing system to disregard interoperability constraints.
摘要翻译： 本发明的一个实施例提出了一种用于在计算统一设备架构（CUDA）应用编程接口（API）和图形API之间共享图形对象的方法。 CUDA API包括用于别名由图形API分配的图形对象的调用，并且随后同步对图形对象的访问。 当应用程序发出针对特定图形对象的注册调用时，CUDA API可确保图形对象位于设备内存中，并将图形对象映射到CUDA地址空间。 随后，当应用程序发出映射和取消映射调用时，CUDA API分别启用和禁用通过CUDA API访问图形对象。 此外，CUDA API使用信号量来同步对共享图形对象的访问。 最后，当应用程序发出未注册的呼叫时，CUDA API将计算系统配置为忽略互操作性约束。
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5.发明授权System and method for enabling interoperability between application programming interfaces 有权用于实现应用程序编程接口之间的互操作性的系统和方法公开(公告)号：US08539516B1
公开(公告)日：2013-09-17
申请号：US12031678
申请日：2008-02-14
摘要： One embodiment of the present invention sets forth a method for sharing graphics objects between a compute unified device architecture (CUDA) application programming interface (API) and a graphics API. The CUDA API includes calls used to alias graphics objects allocated by the graphics API and, subsequently, synchronize accesses to the graphics objects. When an application program emits a “register” call that targets a particular graphics object, the CUDA API ensures that the graphics object is in the device memory, and maps the graphics object into the CUDA address space. Subsequently, when the application program emits “map” and “unmap” calls, the CUDA API respectively enables and disables accesses to the graphics object through the CUDA API. Further, the CUDA API uses semaphores to synchronize accesses to the shared graphics object. Finally, when the application program emits an “unregister” call, the CUDA API configures the computing system to disregard interoperability constraints.
摘要翻译： 本发明的一个实施例提出了一种用于在计算统一设备架构（CUDA）应用编程接口（API）和图形API之间共享图形对象的方法。 CUDA API包括用于别名由图形API分配的图形对象的调用，并且随后同步对图形对象的访问。 当应用程序发出针对特定图形对象的“注册”调用时，CUDA API确保图形对象位于设备内存中，并将图形对象映射到CUDA地址空间。 随后，当应用程序发出“映射”和“映射”调用时，CUDA API分别启用和禁用通过CUDA API访问图形对象。 此外，CUDA API使用信号量来同步对共享图形对象的访问。 最后，当应用程序发出“注销”调用时，CUDA API会将计算系统配置为忽略互操作性约束。
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6.发明授权Generating event signals for performance register control using non-operative instructions 有权使用非操作指令生成用于性能寄存器控制的事件信号公开(公告)号：US07809928B1
公开(公告)日：2010-10-05
申请号：US11313872
申请日：2005-12-20
申请人： Roger L. Allen , Brett W. Coon , Ian A. Buck , John R. Nickolls
发明人： Roger L. Allen , Brett W. Coon , Ian A. Buck , John R. Nickolls
CPC分类号： G06T1/20 , G06F9/30072 , G06F9/30076 , G06F11/3466 , G06F2201/86 , G06F2201/865 , G06F2201/88
摘要： One embodiment of an instruction decoder includes an instruction parser configured to process a first non-operative instruction and to generate a first event signal corresponding to the first non-operative instruction, and a first event multiplexer configured to receive the first event signal from the instruction parser, to select the first event signal from one or more event signals and to transmit the first event signal to an event logic block. The instruction decoder may be implemented in a multithreaded processing unit, such as a shader unit, and the occurrences of the first event signal may be tracked when one or more threads are executed within the processing unit. The resulting event signal count may provide a designer with a better understanding of the behavior of a program, such as a shader program, executed within the processing unit, thereby facilitating overall processing unit and program design.
摘要翻译： 指令解码器的一个实施例包括：指令解析器，被配置为处理第一非操作指令并产生对应于第一非操作指令的第一事件信号;以及第一事件多路复用器，被配置为从指令接收第一事件信号 解析器，以从一个或多个事件信号中选择第一事件信号，并将第一事件信号发送到事件逻辑块。 指令解码器可以在诸如着色器单元的多线程处理单元中实现，并且当在处理单元内执行一个或多个线程时，可以跟踪第一事件信号的出现。 所得到的事件信号计数可以使设计者更好地理解在处理单元内执行的诸如着色器程序之类的程序的行为，从而有助于整体处理单元和程序设计。
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7.发明授权公开(公告)号：US08271763B2
公开(公告)日：2012-09-18
申请号：US12567637
申请日：2009-09-25
IPC分类号： G06F12/10
CPC分类号： G06F12/1054 , G06F12/0284 , G06F12/109 , G06F13/404 , G06F2212/302 , G06F2212/656
摘要： One embodiment of the present invention sets forth a technique for unifying the addressing of multiple distinct parallel memory spaces into a single address space for a thread. A unified memory space address is converted into an address that accesses one of the parallel memory spaces for that thread. A single type of load or store instruction may be used that specifies the unified memory space address for a thread instead of using a different type of load or store instruction to access each of the distinct parallel memory spaces.
摘要翻译： 本发明的一个实施例提出了一种用于将多个不同的并行存储器空间的寻址统一为用于线程的单个地址空间的技术。 统一的存储空间地址被转换为访问该线程的并行存储器空间之一的地址。 可以使用单一类型的加载或存储指令，其指定线程的统一存储器空间地址，而不是使用不同类型的加载或存储指令来访问每个不同的并行存储器空间。
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8.发明申请公开(公告)号：US20110078406A1
公开(公告)日：2011-03-31
申请号：US12567637
申请日：2009-09-25
IPC分类号： G06F12/10
CPC分类号： G06F12/1054 , G06F12/0284 , G06F12/109 , G06F13/404 , G06F2212/302 , G06F2212/656
摘要： One embodiment of the present invention sets forth a technique for unifying the addressing of multiple distinct parallel memory spaces into a single address space for a thread. A unified memory space address is converted into an address that accesses one of the parallel memory spaces for that thread. A single type of load or store instruction may be used that specifies the unified memory space address for a thread instead of using a different type of load or store instruction to access each of the distinct parallel memory spaces.
摘要翻译： 本发明的一个实施例提出了一种用于将多个不同的并行存储器空间的寻址统一为用于线程的单个地址空间的技术。 统一的存储空间地址被转换为访问该线程的并行存储器空间之一的地址。 可以使用单一类型的加载或存储指令，其指定线程的统一存储器空间地址，而不是使用不同类型的加载或存储指令来访问每个不同的并行存储器空间。
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公开(公告)号：US20080184211A1
公开(公告)日：2008-07-31
申请号：US11627892
申请日：2007-01-26
申请人： John R. Nickolls , Henry P. Moreton , Lars S. Nyland , Ian A. Buck , Richard C. Johnson , Robert S. Glanville , Jayant B. Kolhe
发明人： John R. Nickolls , Henry P. Moreton , Lars S. Nyland , Ian A. Buck , Richard C. Johnson , Robert S. Glanville , Jayant B. Kolhe
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A virtual architecture and instruction set support explicit parallel-thread computing. The virtual architecture defines a virtual processor that supports concurrent execution of multiple virtual threads with multiple levels of data sharing and coordination (e.g., synchronization) between different virtual threads, as well as a virtual execution driver that controls the virtual processor. A virtual instruction set architecture for the virtual processor is used to define behavior of a virtual thread and includes instructions related to parallel thread behavior, e.g., data sharing and synchronization. Using the virtual platform, programmers can develop application programs in which virtual threads execute concurrently to process data; virtual translators and drivers adapt the application code to particular hardware on which it is to execute, transparently to the programmer.
摘要翻译： 虚拟架构和指令集支持显式并行线程计算。 虚拟架构定义了支持多个虚拟线程的并行执行的虚拟处理器，该多个虚拟线程具有不同虚拟线程之间的多级数据共享和协调（例如，同步），以及控制虚拟处理器的虚拟执行驱动器。 用于虚拟处理器的虚拟指令集架构用于定义虚拟线程的行为，并且包括与并行线程行为相关的指令，例如数据共享和同步。 使用虚拟平台，程序员可以开发虚拟线程同时执行以处理数据的应用程序; 虚拟翻译器和驱动程序将应用程序代码调整到要执行的特定硬件，对程序员是透明的。
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10.发明授权System, method, and computer program product for compiling code adapted to execute utilizing a first processor, for executing the code utilizing a second processor 有权用于编译适于使用第一处理器执行的代码的系统，方法和计算机程序产品，用于使用第二处理器执行代码公开(公告)号：US08261234B1
公开(公告)日：2012-09-04
申请号：US12032291
申请日：2008-02-15
申请人： Bastiaan J. M. Aarts , Ian A. Buck
发明人： Bastiaan J. M. Aarts , Ian A. Buck
IPC分类号： G06F9/44
CPC分类号： G06F11/3624 , G06F8/45 , G06F8/47
摘要： A system, method, and computer program product are provided for compiling code adapted to execute utilizing a first processor, for executing the code utilizing a second processor. In operation, code adapted to execute utilizing a first processor is identified. Additionally, the code is compiled for executing the code utilizing a second processor that is different from the first processor and includes a central processing unit. Further, the code is executed utilizing the second processor.
摘要翻译： 提供了一种系统，方法和计算机程序产品，用于编译适于使用第一处理器执行的代码，用于使用第二处理器执行代码。 在操作中，识别适于利用第一处理器执行的代码。 另外，代码被编译用于使用与第一处理器不同的第二处理器来执行代码，并且包括中央处理单元。 此外，利用第二处理器执行代码。
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