公开(公告)号：US07418468B2

公开(公告)日：2008-08-26

申请号：US11056063

申请日：2005-02-10

申请人： Chris J. Winstead ,  Christian Schlegel

发明人： Chris J. Winstead ,  Christian Schlegel

IPC分类号： G06F7/52 ,  G06G7/16 ,  H03M13/00

CPC分类号： H03M13/3905 ,  H03M13/1102 ,  H03M13/1134 ,  H03M13/2957 ,  H03M13/6561 ,  H03M13/6597

摘要： Low-voltage CMOS (Complementary Metal Oxide Semiconductor) circuits, suitable for analog decoders, for example, are provided. The circuits include multiplier modules that receive first input signals and respective ones of a plurality of second input signals. Each multiplier module generates as output signals products of the first input signals and its respective second input signals. Dummy multiplier modules that respectively correspond to the multiplier modules receive the second input signals, and each dummy multiplier module forms products of the second input signal of its corresponding multiplier module and the other second input signals. The dummy multiplier modules reduce the overall voltage requirements of the circuit, thereby providing for low-voltage operation. In some embodiments, a connectivity module receives output signals from the multiplier modules and generates as output signals sums of predetermined ones of the output signals, and a renormalization module receives and normalizes the output signals from the connectivity module to generate output signals that sum to a predetermined unit value.

摘要翻译： 提供了适用于模拟解码器的低电压CMOS（互补金属氧化物半导体）电路。 电路包括接收第一输入信号和多个第二输入信号中相应的乘法器模块。 每个乘法器模块产生第一输入信号及其相应的第二输入信号的输出信号的产物。 分别对应于乘法器模块的虚拟乘法器模块接收第二输入信号，并且每个虚拟乘法器模块形成其对应的乘法器模块的第二输入信号和其它第二输入信号的乘积。 虚拟乘法器模块降低了电路的总体电压要求，从而提供低电压操作。 在一些实施例中，连接模块接收来自乘法器模块的输出信号，并且产生作为输出信号的预定输出信号的和的重新归一化模块接收和归一化来自连接模块的输出信号，以产生与 预定单位价值。