公开(公告)号：US08898537B2

公开(公告)日：2014-11-25

申请号：US13050065

申请日：2011-03-17

Applicant: Warren Gross ,  Francois Leduc-Primeau ,  Saied Hemati ,  Shie Mannor

Inventor： Warren Gross ,  Francois Leduc-Primeau ,  Saied Hemati ,  Shie Mannor

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/25

CPC classification number: H03M13/255 ,  H03M13/1111 ,  H03M13/1125 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/6544 ,  H03M13/658 ,  H03M13/6597

Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. LDPC codes also offer error correction performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with the code length. They also offer challenges relating to the decoding complexity of the binary error-correction codes themselves and error floors limiting achievable bit-error rates. A new Relaxed Half-Stochastic (RHS) decoding algorithm is presented that reduces decoding complexity for high decoding throughput applications. The RHS algorithm uses an approach based on stochastic decoding algorithms but differs significantly from the conventional approaches of LDPC decoder implementation. The RHS algorithm also leads to a randomized decoding technique called redecoding that addresses the error floor limitation.

Abstract translation: 低密度奇偶校验（LDPC）码在接近链路信道容量的速率下提供误码校正，并且在存在数据破坏噪声的带宽或返回信道受限链路上进行可靠和有效的信息传输。 LDPC码还提供了在代码长度，线性处理复杂度和与代码长度相关联的并行性方面，指数速度接近信道容量的纠错性能。 它们还提供与二进制纠错码本身的解码复杂性相关的挑战，并且限制可实现的误码率的错误层。 提出了一种新的轻便半随机（RHS）解码算法，降低了高解码吞吐量应用的解码复杂度。 RHS算法使用基于随机解码算法的方法，但与LDPC解码器实现的传统方法有很大的不同。 RHS算法还导致称为重新编码的随机解码技术，其解决错误楼层限制。

公开(公告)号：US20110255612A1

公开(公告)日：2011-10-20

申请号：US13032520

申请日：2011-02-22

Applicant: Jeffrey Bernstein ,  Benjamin Vigoda ,  David Reynolds ,  Alexander Alexeyev ,  William Bradley

Inventor： Jeffrey Bernstein ,  Benjamin Vigoda ,  David Reynolds ,  Alexander Alexeyev ,  William Bradley

IPC: H04L27/00

CPC classification number: H03M13/6597 ,  H03M13/1111

Abstract: A processor implements a network of functional nodes and communication paths between the nodes. The processor includes a plurality of circuit implementations of the functional nodes of the processor; and a plurality of signal paths implementing the communication paths linking the circuit implementations of the nodes. At least some of the signal paths are configured to pass signal values represented according to temporal patterns of signal levels on the signal paths. The processor also includes a plurality of circuit components for conversion between a signal value represented as a signal level (e.g., voltage or current level) and a signal value represented as a temporal pattern.

Abstract translation: 处理器实现节点之间的功能节点和通信路径的网络。 处理器包括处理器的功能节点的多个电路实现; 以及实现链接节点的电路实现的通信路径的多个信号路径。 至少一些信号路径被配置为传递根据信号路径上的信号电平的时间模式表示的信号值。 处理器还包括用于在表示为信号电平（例如，电压或电流电平）的信号值和表示为时间模式的信号值之间进行转换的多个电路部件。

公开(公告)号：US20110231731A1

公开(公告)日：2011-09-22

申请号：US13050065

申请日：2011-03-17

Applicant: Warren Gross ,  Francois Leduc-Primeau ,  Saied Hemati ,  Shie Mannor

Inventor： Warren Gross ,  Francois Leduc-Primeau ,  Saied Hemati ,  Shie Mannor

IPC: H03M13/00 ,  G06F11/08

CPC classification number: H03M13/255 ,  H03M13/1111 ,  H03M13/1125 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/6544 ,  H03M13/658 ,  H03M13/6597

Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. LDPC codes also offer error correction performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with the code length. They also offer challenges relating to the decoding complexity of the binary error-correction codes themselves and error floors limiting achievable bit-error rates. A new Relaxed Half-Stochastic (RHS) decoding algorithm is presented that reduces decoding complexity for high decoding throughput applications. The RHS algorithm uses an approach based on stochastic decoding algorithms but differs significantly from the conventional approaches of LDPC decoder implementation. The RHS algorithm also leads to a randomized decoding technique called redecoding that addresses the error floor limitation.

Abstract translation: 低密度奇偶校验（LDPC）码在接近链路信道容量的速率下提供误码校正，并且在存在数据破坏噪声的带宽或返回信道受限链路上进行可靠和有效的信息传输。 LDPC码还提供了在代码长度，线性处理复杂性和与代码长度相关联的并行性方面，指数速度接近信道容量的纠错性能。 它们还提供与二进制纠错码本身的解码复杂性相关的挑战，并且限制可实现的误码率的错误层。 提出了一种新的轻便半随机（RHS）解码算法，降低了高解码吞吐量应用的解码复杂度。 RHS算法使用基于随机解码算法的方法，但与LDPC解码器实现的传统方法有很大的不同。 RHS算法还导致称为重新编码的随机解码技术，其解决错误楼层限制。

公开(公告)号：US07860687B2

公开(公告)日：2010-12-28

申请号：US11738696

申请日：2007-04-23

Applicant: Benjamin Vigoda ,  Neil Gershenfeld

Inventor： Benjamin Vigoda ,  Neil Gershenfeld

IPC: G06F9/00 ,  G06F7/00 ,  G06F17/00

CPC classification number: H03M13/37 ,  G06J1/00 ,  H03M13/6597

Abstract: Methods for applications such as signal processing, analysis, and coding/decoding replace digital signal processing elements with analog components are implemented by combining soft logic gates and filters, permitting the functionality of complex finite state machines to be implemented.

Abstract translation: 通过组合软逻辑门和滤波器来实现用模拟组件代替数字信号处理元件的信号处理，分析和编码/解码等应用方法，从而实现复杂有限状态机的功能。

公开(公告)号：US20100281348A1

公开(公告)日：2010-11-04

申请号：US12432609

申请日：2009-04-29

Applicant: Matthias Bussmann ,  Salam Elahmadi

Inventor： Matthias Bussmann ,  Salam Elahmadi

IPC: H03M13/03

CPC classification number: H03M13/4107 ,  H03M13/41 ,  H03M13/6597

Abstract: One embodiment of the invention features a programmable gain stage in analog update circuitry to overcome the accuracy limitation of the circuit gain and the maintenance of small finite number of possible sequence estimates.

Abstract translation: 本发明的一个实施例的特征在于模拟更新电路中的可编程增益级，以克服电路增益的精度限制和维持小有限数量的可能序列估计。

公开(公告)号：US20100281337A1

公开(公告)日：2010-11-04

申请号：US12431917

申请日：2009-04-29

Applicant: Ming Yam Lo ,  Wai Ho Mow ,  Wing Hung Ki

Inventor： Ming Yam Lo ,  Wai Ho Mow ,  Wing Hung Ki

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/11 ,  H03M13/6597

Abstract: An iterative decoder comprising a transconductance amplifier, a sampler, a Min-Sum decoder, and an early determination module is provided. The transconductance amplifier outputs a current proportional to the voltage of the coded bit stream. The sampler converts the amplified current into a plurality of currents and stores the sampled currents in a plurality of buffers. The Min-Sum decoder receives parallel currents, wherein currents represent the message of each variable node. The Min-Sum decoder exchanges the message of variable nodes and check nodes iteratively and outputs a set of decode codewords according to the possibilities. The early terminating module stops the iterative decoding when the decoded codeword converged.

Abstract translation: 提供了包括跨导放大器，采样器，最小和解码器和早期确定模块的迭代解码器。 跨导放大器输出与编码比特流的电压成比例的电流。 采样器将放大的电流转换成多个电流并将采样的电流存储在多个缓冲器中。 最小和解码器接收并行电流，其中电流表示每个变量节点的消息。 Min-Sum解码器迭代地交换变量节点和校验节点的消息，并根据可能性输出一组解码码字。 当解码的码字收敛时，早期终接模块停止迭代解码。

公开(公告)号：US20070011573A1

公开(公告)日：2007-01-11

申请号：US11442485

申请日：2006-05-26

Applicant: Ramin Farjadrad ,  Ramin Shirani

Inventor： Ramin Farjadrad ,  Ramin Shirani

IPC: H03M13/00

CPC classification number: H03M13/6597 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/2975 ,  H03M13/3738

Abstract: A decoder architecture and method for implementing a decoder are provided. In one implementation, the decoder architecture includes an input buffer configured to receive a plurality of codewords to be processed, and includes an iterative decoder configured to receive a first codeword from the input buffer and process the first codeword. The iterative decoder processes the first codeword only for an amount of time required for the first codeword to become substantially error free. The decoder architecture further includes logic coupled to each of the iterative decoder and the input buffer. The logic is configured to determine when the first codeword processed by the decoder becomes substantially error free. The logic further generates a signal for loading a second codeword from the input buffer into the iterative decoder responsive to the logic determining when the first codeword becomes substantially error free.

Abstract translation: 提供了一种用于实现解码器的解码器架构和方法。 在一个实现中，解码器架构包括被配置为接收待处理的多个码字的输入缓冲器，并且包括被配置为从输入缓冲器接收第一码字并处理第一码字的迭代解码器。 迭代解码器只处理第一码字所需的时间量变得基本上无差错的第一码字。 解码器架构还包括耦合到每个迭代解码器和输入缓冲器的逻辑。 逻辑被配置为确定由解码器处理的第一码字何时基本上无错误。 该逻辑进一步产生用于将第二代码字从输入缓冲器加载到迭代解码器中的信号，该逻辑确定何时第一代码字基本上无错误。

公开(公告)号：US06374385B1

公开(公告)日：2002-04-16

申请号：US09318247

申请日：1999-05-25

Applicant: Ari Hämäläinen ,  Jukka Henriksson

Inventor： Ari Hämäläinen ,  Jukka Henriksson

IPC: H03M1303

CPC classification number: H03M13/6516 ,  H03M13/23 ,  H03M13/39 ,  H03M13/41 ,  H03M13/6597

Abstract: The invention relates to a method and an arrangement for decoding a convolutionally encoded signal which comprises code words and the arrangement comprises a neural network which comprises a set of neurons comprising a set of inputs and an output. The received code words are applied to the inputs of the neurons, and the arrangement combines some of the inputs of the neuron in the neuron. In order to enable efficient decoding of the convolutional encoding, some of the output signals of the neural network neurons are fed back to the inputs of the neuron and the neuron multiplies at least some of the inputs of the neuron with one another before combining. The output signal of a predetermined neuron comprises an estimate of a decoded symbol.

Abstract translation: 本发明涉及用于解码包括码字的卷积编码信号的方法和装置，并且该装置包括神经网络，神经网络包括一组包括一组输入和输出的神经元。 接收到的码字被应用于神经元的输入，并且该装置将神经元中的神经元的一些输入结合在一起。 为了能够进行卷积编码的有效解码，将神经网络神经元的一些输出信号反馈给神经元的输入，并且神经元在组合之前将神经元的至少一些输入彼此相乘。 预定神经元的输出信号包括解码符号的估计。

公开(公告)号：US5933463A

公开(公告)日：1999-08-03

申请号：US759245

申请日：1996-12-02

Applicant: Davy H. Choi

Inventor： Davy H. Choi

IPC: G11B20/10 ,  H03M13/41 ,  H04L25/06 ,  H03D1/00 ,  H04L27/06

CPC classification number: H03M13/6597 ,  G11B20/10009 ,  H03M13/4107 ,  H04L25/067

Abstract: A method and circuit for generating an updated metric signal for an analog Viterbi detector is disclosed. A circuit in accordance with the invention comprises a first summing amplifier 11 for subtracting a first reference voltage from a data signal; a second summing amplifier 12 for subtracting a second reference voltage from the data signal; a first comparator 21 for comparing the output of the first summing amplifier with a previous metric signal; a second comparator 22 for comparing the output of the second summing amplifier with the previous metric signal; a first AND gate 41 for combining the output of the first comparator and a first clock signal; a second AND gate 42 for combining the output of the second comparator and the first clock signal; a first sample-and-hold device 51 for sampling the output of the first summing amplifier 11 in response to the output of the first AND gate 41; and a second sample-and-hold device 52 for sampling the output of the second summing amplifier 12 in response to the output of the second AND gate 42. The updated metric signal is output on node 70. A holding capacitor 60 retains a charge associated with the updated metric signal during clock cycles when sample-and-hold circuits 51 and 52 are not triggered.

Abstract translation: 公开了一种用于产生用于模拟维特比检测器的更新的度量信号的方法和电路。 根据本发明的电路包括：第一求和放大器11，用于从数据信号中减去第一参考电压; 第二加法放大器12，用于从数据信号中减去第二参考电压; 第一比较器21，用于将第一求和放大器的输出与先前的度量信号进行比较; 第二比较器22，用于将第二加法放大器的输出与先前的度量信号进行比较; 第一与门41，用于组合第一比较器的输出和第一时钟信号; 第二与门42，用于组合第二比较器的输出和第一时钟信号; 第一采样保持装置51，用于响应于第一与门41的输出对第一求和放大器11的输出进行采样; 以及第二取样和保持装置52，用于响应于第二与门42的输出对第二求和放大器12的输出进行采样。更新的度量信号在节点70上输出。保持电容器60保持与电荷相关的电荷 当采样保持电路51和52未被触发时，在时钟周期期间具有更新的度量信号。

公开(公告)号：US12063052B2

公开(公告)日：2024-08-13

申请号：US18482964

申请日：2023-10-09

Applicant: Hewlett Packard Enterprise Development LP

Inventor： John Paul Strachan ,  Catherine Graves ,  Can Li

IPC: H03M13/00 ,  G11C13/00 ,  H03M13/15 ,  G11C27/00 ,  H03M13/11

CPC classification number: H03M13/6597 ,  G11C13/004 ,  H03M13/1575 ,  G11C13/0069 ,  G11C27/005 ,  H03M13/1177

Abstract: An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other non-volatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.