公开(公告)号：US20080037342A1

公开(公告)日：2008-02-14

申请号：US11876477

申请日：2007-10-22

申请人： Chris Martin ,  Troy Manning ,  Brent Keeth

发明人： Chris Martin ,  Troy Manning ,  Brent Keeth

IPC分类号： G11C7/00 ,  G11C17/18

CPC分类号： G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

摘要翻译： 用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。 第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。 当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

公开(公告)号：US20070153595A1

公开(公告)日：2007-07-05

申请号：US11714979

申请日：2007-03-07

申请人： Chris Martin ,  Troy Manning ,  Brent Keeth

发明人： Chris Martin ,  Troy Manning ,  Brent Keeth

IPC分类号： G11C29/00

CPC分类号： G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

公开(公告)号：US07404124B2

公开(公告)日：2008-07-22

申请号：US11712040

申请日：2007-02-28

申请人： Chris Martin ,  James Brian Johnson ,  Troy Manning ,  Brent Keeth

发明人： Chris Martin ,  James Brian Johnson ,  Troy Manning ,  Brent Keeth

IPC分类号： G01R31/28

CPC分类号： G11C29/48 ,  G11C29/1201

摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

摘要翻译： 通过寻址电路，采样电路可以在封装/封装的芯片上选择唯一的内部节点/信号，以输出到一个或多个驱动器。 在目标节点处可用的选定信号通过选择电路指向输出引脚，或直接指向输出引脚。 在优选模式中，用于选择唯一节点的解码电路串联连接，允许大量的信号可用于分析，而不会对电路布局造成很大影响。 由于与摘要相关的规则，本摘要不应用于索赔的构建。

公开(公告)号：US20070168796A1

公开(公告)日：2007-07-19

申请号：US11712041

申请日：2007-02-28

申请人： Chris Martin ,  James Johnson ,  Troy Manning ,  Brent Keeth

发明人： Chris Martin ,  James Johnson ,  Troy Manning ,  Brent Keeth

IPC分类号： G01R31/28

CPC分类号： G11C29/48 ,  G11C29/1201

摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

公开(公告)号：US20050047228A1

公开(公告)日：2005-03-03

申请号：US10966746

申请日：2004-10-15

申请人： Brent Keeth ,  Troy Manning ,  Chris Martin ,  Ebrahim Hargan

发明人： Brent Keeth ,  Troy Manning ,  Chris Martin ,  Ebrahim Hargan

IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C29/00

CPC分类号： G11C29/848

摘要： A system and method for selecting redundant rows and columns of memory devices includes a column select steering circuit to couple column select signals from a column address decoder to an array of memory cells. The system and method also includes a fuse banks for programming respective addresses of up to two defective columns that are to be repaired. The programmed addresses are applied to a defective column decoder that determines which column select signal(s) should be shifted downwardly and which column select signal(s) should be shifted upwardly. The column select steering circuit responds to signals from the defective column decoder to shift the column select signals downwardly or upwardly. The column select signal for the lowest column is shifted downwardly to a redundant column, and the column select signal for the highest column is shifted upwardly to a redundant column.

摘要翻译： 用于选择存储器件的冗余行和列的系统和方法包括：列选择转向电路，用于将列选择信号从列地址解码器耦合到存储器单元阵列。 该系统和方法还包括用于编程待修复的多达两个缺陷列的相应地址的熔丝组。 编程的地址被应用于有缺陷的列解码器，该解码器确定哪个列选择信号应该被向下移位，哪个列选择信号应向上移位。 列选择转向电路响应来自故障列解码器的信号，以向下或向上移动列选择信号。 最低列的列选择信号向下移动到冗余列，最高列的列选择信号向上移动到冗余列。

公开(公告)号：US20060236170A1

公开(公告)日：2006-10-19

申请号：US11109535

申请日：2005-04-19

申请人： Chris Martin ,  James Johnson ,  Troy Manning ,  Brent Keeth

发明人： Chris Martin ,  James Johnson ,  Troy Manning ,  Brent Keeth

IPC分类号： G01R31/28

CPC分类号： G11C29/48 ,  G11C29/1201

摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

摘要翻译： 通过寻址电路，采样电路可以在封装/封装的芯片上选择唯一的内部节点/信号，以输出到一个或多个驱动器。 在目标节点处可用的选定信号通过选择电路指向输出引脚，或直接指向输出引脚。 在优选模式中，用于选择唯一节点的解码电路串联连接，允许大量的信号可用于分析，而不会对电路布局造成很大影响。 由于与摘要相关的规则，本摘要不应用于索赔的构建。

公开(公告)号：US07412634B2

公开(公告)日：2008-08-12

申请号：US11712041

申请日：2007-02-28

申请人： Chris Martin ,  James Brian Johnson ,  Troy Manning ,  Brent Keeth

发明人： Chris Martin ,  James Brian Johnson ,  Troy Manning ,  Brent Keeth

IPC分类号： G01R31/28

CPC分类号： G11C29/48 ,  G11C29/1201

摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

公开(公告)号：US07251762B2

公开(公告)日：2007-07-31

申请号：US11109535

申请日：2005-04-19

申请人： Chris Martin ,  James Brian Johnson ,  Troy Manning ,  Brent Keeth

发明人： Chris Martin ,  James Brian Johnson ,  Troy Manning ,  Brent Keeth

IPC分类号： G01R31/28

CPC分类号： G11C29/48 ,  G11C29/1201

摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout.

摘要翻译： 通过寻址电路，采样电路可以在封装/封装的芯片上选择唯一的内部节点/信号，以输出到一个或多个驱动器。 在目标节点处可用的选定信号通过选择电路指向输出引脚，或直接指向输出引脚。 在优选模式中，用于选择唯一节点的解码电路串联连接，允许大量的信号可用于分析，而不会对电路布局造成很大影响。

公开(公告)号：US20070168795A1

公开(公告)日：2007-07-19

申请号：US11712040

申请日：2007-02-28

申请人： Chris Martin ,  James Johnson ,  Troy Manning ,  Brent Keeth

发明人： Chris Martin ,  James Johnson ,  Troy Manning ,  Brent Keeth

IPC分类号： G01R31/28

CPC分类号： G11C29/48 ,  G11C29/1201

摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

摘要翻译： 通过寻址电路，采样电路可以在封装/封装的芯片上选择唯一的内部节点/信号，以输出到一个或多个驱动器。 在目标节点处可用的选定信号通过选择电路指向输出引脚，或直接指向输出引脚。 在优选模式中，用于选择唯一节点的解码电路串联连接，允许大量的信号可用于分析，而不会对电路布局造成很大影响。 由于与摘要相关的规则，本摘要不应用于索赔的构建。

公开(公告)号：US20070002646A1

公开(公告)日：2007-01-04

申请号：US11170260

申请日：2005-06-29

申请人： Chris Martin ,  Troy Manning ,  Brent Keeth

发明人： Chris Martin ,  Troy Manning ,  Brent Keeth

IPC分类号： G11C29/00

CPC分类号： G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.