Synchronization system for a semi-digital signal
    3.
    发明授权
    Synchronization system for a semi-digital signal 失效
    半数字信号同步系统

    公开(公告)号:US4860100A

    公开(公告)日:1989-08-22

    申请号:US154178

    申请日:1988-02-08

    CPC classification number: H04N11/08 H04N7/083

    Abstract: A system which provides synchronization with frame synchronization words of a partially digital signal, such as that of the D2MAC television standard. It is provided that three modes of operation are established sequentially. In a first mode, the values necessary to control the gain and the d.c. level of the television signal are obtained by means of a peak detector (18). Similarly, in a second mode, the peak detector is enabled only during the digital signal periods of the D2MAC signal. Finally, in the third mode, the setting values are obtained by arrangements (13, 8) which depend on the clamp plateau measurement of each line and of line 624. The television signal is converted into a digital signal by an analog/digital converter (6), which, more specifically, feeds the digital arrangement (8) for measuring the picture plateaus; the results of the peak detector measurement (18) are also converted into digital values (17), managing the procedure and the processing of at least a portion of the control signals is effected by a microprocessor (33) and certain control signals are again converted into analog values by a digital/analog converter (10).

    Abstract translation: 提供与部分数字信号的帧同步字(例如D2MAC电视标准的帧同步字)同步的系统。 提供了顺序建立三种操作模式。 在第一种模式下,控制增益和直流电压所需的值。 通过峰值检测器(18)获得电视信号的电平。 类似地,在第二模式中,峰值检测器仅在D2MAC信号的数字信号周期期间使能。 最后,在第三模式中,通过依赖于每条线路和线路624的钳位平台测量的布置(13,8)获得设定值。电视信号由模拟/数字转换器转换成数字信号 6),更具体地,馈送用于测量图像平台的数字排列(8); 峰值检测器测量(18)的结果也被转换成数字值(17),管理过程,并且至少一部分控制信号的处理由微处理器(33)实现,并且某些控制信号被再次转换 由数字/模拟转换器(10)转换为模拟值。

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