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公开(公告)号：US20110320783A1
公开(公告)日：2011-12-29
申请号：US12822417
申请日：2010-06-24
IPC分类号： G06F9/30
CPC分类号： G06F17/504 , G06F9/30 , G06F11/3636 , G06F11/3648
摘要： A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding opcode from the chosen instruction and initializing Opcode Compare logic to trap the chosen instruction to firmware and creating firmware to initiate performance of hardware verification in the firmware and re-initiating performance of the hardware verification in hardware.
摘要翻译： 提供了一种验证方法，包括在预定义的程序中随机选择硬件执行指令以强制运行代码比较，根据所选择的指令确定相应操作码的标识，并初始化操作码比较逻辑，将所选指令陷入固件并创建固件 启动硬件验证的性能，并重新启动硬件验证的性能。
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公开(公告)号：US09218442B2
公开(公告)日：2015-12-22
申请号：US12822417
申请日：2010-06-24
CPC分类号： G06F17/504 , G06F9/30 , G06F11/3636 , G06F11/3648
摘要： A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding opcode from the chosen instruction and initializing Opcode Compare logic to trap the chosen instruction to firmware and creating firmware to initiate performance of hardware verification in the firmware and re-initiating performance of the hardware verification in hardware.
摘要翻译： 提供了一种验证方法，包括在预定义的程序中随机选择硬件执行指令以强制运行代码比较，根据所选择的指令确定相应操作码的标识，并初始化操作码比较逻辑，将所选指令陷入固件并创建固件 启动硬件验证的性能，并重新启动硬件验证的性能。
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公开(公告)号：US20090210387A1
公开(公告)日：2009-08-20
申请号：US12033974
申请日：2008-02-20
IPC分类号： G06F17/30
CPC分类号： G06F17/5045 , G06F2217/68
摘要： A system includes a storage device including a human readable common instruction table (CIT) stored as a text file. The system also includes CIT access software for performing a method including receiving a request from a first user for all or a subset of the CIT table relating to logic design and for providing the requested data to the first user. The method also includes receiving a request from a second user is received for all or a subset of the CIT table relating to performance analysis and for providing the requested data to the second user. A request is received from a third user for all or a subset of the CIT data relating to design verification and the requested data is provided to the third user.
摘要翻译： 系统包括存储装置，该存储装置包括作为文本文件存储的人可读公用指令表（CIT）。 该系统还包括用于执行方法的CIT访问软件，该方法包括从第一用户接收与逻辑设计相关的CIT表的全部或子集的请求，以及向第一用户提供所请求的数据。 该方法还包括接收来自与用于性能分析相关的CIT表的全部或子集的第二用户的请求，以及向第二用户提供所请求的数据。 对于与设计验证相关的CIT数据的全部或子集，从第三用户接收请求，并且将所请求的数据提供给第三用户。
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4.发明授权Method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model 失效在模拟模型中处理指令拒绝，部分拒绝，停止和分支错误的方法和装置公开(公告)号：US08484007B2
公开(公告)日：2013-07-09
申请号：US12032647
申请日：2008-02-16
IPC分类号： G06F17/50
CPC分类号： G06F9/3861 , G06F9/455
摘要： A method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model provides pipeline states for various unit verification. It defines an instruction train to encounter many events of the hardware verifications. Drivers and monitors at a unit and a core simulation level can hook into the pipeline states and perform the verification easily without having to restructure the instructions in the pipeline due to rejects, partial rejects, stalls, branch wrongs. Different event counters have been placed in the instruction pipe during the events and expand the instruction train such that the instruction train provides an accurate and detailed state of each instruction so the hardware logic signals and data can be tracked and identified from each state.
摘要翻译： 在模拟模型中处理指令拒绝，部分拒绝，停顿和分支错误的方法和装置提供用于各种单元验证的流水线状态。 它定义了一个指令列表，以遇到许多硬件验证事件。 单元和核心模拟级别的驱动程序和监视器可以挂钩到管道状态，并且容易地执行验证，而不必由于拒绝，部分拒绝，停顿，分支错误而重新组织管道中的指令。 在事件期间，不同的事件计数器被放置在指令管道中，并扩展指令序列，使得指令串提供每个指令的准确和详细的状态，从而可以从每个状态追踪和识别硬件逻辑信号和数据。
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5.发明授权Method, system and computer program product for verifying address generation, interlocks and bypasses 有权用于验证地址生成，互锁和旁路的方法，系统和计算机程序产品公开(公告)号：US08165864B2
公开(公告)日：2012-04-24
申请号：US12028038
申请日：2008-02-08
CPC分类号： G06F11/261 , G06F9/3824 , G06F9/3826
摘要： Method, system and computer program product for verifying the address generation, address generation interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values from a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, selecting a second set of general purpose register values, updating the first set of general purpose register values with the second set of general purpose register values and placing the second set of general purpose register values on a bus.
摘要翻译： 方法，系统和计算机程序产品，用于验证CPU中的地址生成，地址生成互锁和地址生成旁路控制。 示例性实施例包括处理器中的验证方法，该方法包括将第一集合通用寄存器值从第一指令传播到第二指令，其中模拟监视器耦合到指令流水线的第一级，并且其中第一 一组通用寄存器值存储在模拟指令对象中，选择第二组通用寄存器值，用第二组通用寄存器值更新第一组通用寄存器值，并将第二组通用寄存器值 在总线上注册值。
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公开(公告)号：US07895538B2
公开(公告)日：2011-02-22
申请号：US12033974
申请日：2008-02-20
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/68
摘要： A system includes a storage device including a human readable common instruction table (CIT) stored as a text file. The system also includes CIT access software for performing a method including receiving a request from a first user for all or a subset of the CIT table relating to logic design and for providing the requested data to the first user. The method also includes receiving a request from a second user is received for all or a subset of the CIT table relating to performance analysis and for providing the requested data to the second user. A request is received from a third user for all or a subset of the CIT data relating to design verification and the requested data is provided to the third user.
摘要翻译： 系统包括存储装置，该存储装置包括作为文本文件存储的人可读公用指令表（CIT）。 该系统还包括用于执行方法的CIT访问软件，该方法包括从第一用户接收与逻辑设计相关的CIT表的全部或子集的请求，以及向第一用户提供所请求的数据。 该方法还包括接收来自与用于性能分析相关的CIT表的全部或子集的第二用户的请求，以及向第二用户提供所请求的数据。 对于与设计验证相关的CIT数据的全部或子集，从第三用户接收请求，并且将所请求的数据提供给第三用户。
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7.发明申请Method and Apparatus of Handling Instruction Rejects, Partial Rejects, Stalls and Branch Wrong in a Simulation Model 失效在模拟模型中处理指令拒绝，部分拒绝，失败和分支错误的方法和装置公开(公告)号：US20090210681A1
公开(公告)日：2009-08-20
申请号：US12032647
申请日：2008-02-16
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/455
摘要： A method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model provides pipeline states for various unit verification. It defines an instruction train to encounter many events of the hardware verifications. Drivers and monitors at a unit and a core simulation level can hook into the pipeline states and perform the verification easily without having to restructure the instructions in the pipeline due to rejects, partial rejects, stalls, branch wrongs. Different event counters have been placed in the instruction pipe during the events and expand the instruction train such that the instruction train provides an accurate and detailed state of each instruction so the hardware logic signals and data can be tracked and identified from each state.
摘要翻译： 在模拟模型中处理指令拒绝，部分拒绝，停顿和分支错误的方法和装置提供用于各种单元验证的流水线状态。 它定义了一个指令列表，以遇到许多硬件验证事件。 单元和核心模拟级别的驱动程序和监视器可以挂钩到管道状态，并且容易地执行验证，而不必由于拒绝，部分拒绝，停顿，分支错误而重新组织管道中的指令。 在事件期间，不同的事件计数器被放置在指令管道中，并扩展指令序列，使得指令串提供每个指令的准确和详细的状态，从而可以从每个状态追踪和识别硬件逻辑信号和数据。
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8.发明申请METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR VERIFYING ADDRESS GENERATION, INTERLOCKS AND BYPASSES 有权方法，系统和计算机程序产品，用于验证地址生成，互连和旁路公开(公告)号：US20090204796A1
公开(公告)日：2009-08-13
申请号：US12028038
申请日：2008-02-08
IPC分类号： G06F9/30
CPC分类号： G06F11/261 , G06F9/3824 , G06F9/3826
摘要： Method, system and computer program product for verifying the address generation, address generation, interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values fern a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, selecting a second set of general purpose register values, updating the first set of general purpose register values with the second set of general purpose register values and placing the second, set of general purpose register values on a bus.
摘要翻译： 方法，系统和计算机程序产品，用于验证CPU中的地址生成，地址生成，互锁和地址生成旁路控制。 示例性实施例包括处理器中的验证方法，所述方法包括将第一组通用寄存器值蕨类化第一指令传播到第二指令，其中所述模拟监视器耦合到所述指令流水线的第一级，并且其中所述第一 通用寄存器值集合存储在模拟指令对象中，选择第二组通用寄存器值，用第二组通用寄存器值更新第一组通用寄存器值，并将第二组通用寄存器值 总线上的目的寄存器值。
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