公开(公告)号：US20110320783A1

公开(公告)日：2011-12-29

申请号：US12822417

申请日：2010-06-24

申请人： Christopher A. Krygowski ,  Michael P. Mullen ,  Timothy J. Slegel ,  Kai Weber

发明人： Christopher A. Krygowski ,  Michael P. Mullen ,  Timothy J. Slegel ,  Kai Weber

IPC分类号： G06F9/30

CPC分类号： G06F17/504 ,  G06F9/30 ,  G06F11/3636 ,  G06F11/3648

摘要： A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding opcode from the chosen instruction and initializing Opcode Compare logic to trap the chosen instruction to firmware and creating firmware to initiate performance of hardware verification in the firmware and re-initiating performance of the hardware verification in hardware.

摘要翻译： 提供了一种验证方法，包括在预定义的程序中随机选择硬件执行指令以强制运行代码比较，根据所选择的指令确定相应操作码的标识，并初始化操作码比较逻辑，将所选指令陷入固件并创建固件 启动硬件验证的性能，并重新启动硬件验证的性能。

公开(公告)号：US09218442B2

公开(公告)日：2015-12-22

申请号：US12822417

申请日：2010-06-24

申请人： Christopher A. Krygowski ,  Michael P. Mullen ,  Timothy J. Slegel ,  Kai Weber

发明人： Christopher A. Krygowski ,  Michael P. Mullen ,  Timothy J. Slegel ,  Kai Weber

IPC分类号： G06F9/30 ,  G06F17/50 ,  G06F11/36

CPC分类号： G06F17/504 ,  G06F9/30 ,  G06F11/3636 ,  G06F11/3648

摘要： A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding opcode from the chosen instruction and initializing Opcode Compare logic to trap the chosen instruction to firmware and creating firmware to initiate performance of hardware verification in the firmware and re-initiating performance of the hardware verification in hardware.

摘要翻译： 提供了一种验证方法，包括在预定义的程序中随机选择硬件执行指令以强制运行代码比较，根据所选择的指令确定相应操作码的标识，并初始化操作码比较逻辑，将所选指令陷入固件并创建固件 启动硬件验证的性能，并重新启动硬件验证的性能。

公开(公告)号：US20120284007A1

公开(公告)日：2012-11-08

申请号：US13552634

申请日：2012-07-18

申请人： Stefan Letz ,  Kai Weber ,  Juergen Vielfort

发明人： Stefan Letz ,  Kai Weber ,  Juergen Vielfort

IPC分类号： G06F17/50

CPC分类号： G06F9/3859 ,  G06F17/5022 ,  G06F2217/68

摘要： An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein the maintained information includes a determination of an execution length of a completely executed instruction, matching the maintained information about the completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.

摘要翻译： 公开了一种使用仿真环境中的处理器仿真模型验证处理器设计的改进方法，其中所述处理器仿真模型包括用于执行测试文件的至少一个指令的至少一个执行单元。 该方法包括跟踪每个执行至少一个指令中的每一个，监视每个模拟周期中的相关信号，维护关于至少一个指令的执行的信息，其中维护的信息包括完全执行的执行长度的确定 指令，将关于完全执行的指令的维护信息与由用户通过陷阱文件提供的一组陷阱元素相匹配，并且响应于在维护信息之间找到的匹配而将关于完全执行的指令的维护信息收集在监视文件中 和至少一个捕获元件。

公开(公告)号：US07865793B2

公开(公告)日：2011-01-04

申请号：US12113116

申请日：2008-04-30

申请人： Stefan Letz ,  Juergen Vielfort ,  Kai Weber

发明人： Stefan Letz ,  Juergen Vielfort ,  Kai Weber

IPC分类号： G01R31/28 ,  G06F11/00 ,  G06F7/38 ,  G06F9/44

CPC分类号： G06F11/3688

摘要： A method of generating a test case from a given test case structure, the method including generating instructions for the given test case structure, propagating predefined results in a backwards manner, randomly generating remaining operands of the test case structure in a forwards manner, and calculating a result for the test case by determining missing input operands and storing these input operands in both the temporary register file and the initial register file, and calculating missing results and storing all results in the temporary register file.

摘要翻译： 一种从给定的测试用例结构生成测试用例的方法，该方法包括生成给定的测试用例结构的指令，以向后的方式传播预定义的结果，以向前的方式随机生成测试用例结构的剩余操作数，以及计算 通过确定缺少的输入操作数并将这些输入操作数存储在临时寄存器文件和初始寄存器文件中，并计算缺失的结果并将所有结果存储在临时寄存器文件中，这是测试用例的结果。

公开(公告)号：US20080092097A1

公开(公告)日：2008-04-17

申请号：US11963264

申请日：2007-12-21

申请人： CHRISTIAN JACOBI ,  Geert Janssen ,  Viresh Paruthi ,  Kai Weber

发明人： CHRISTIAN JACOBI ,  Geert Janssen ,  Viresh Paruthi ,  Kai Weber

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.

公开(公告)号：US20070011633A1

公开(公告)日：2007-01-11

申请号：US11385928

申请日：2006-03-21

申请人： Kai Weber ,  Christian Jacobi ,  Nico Gulden ,  Viresh Paruthi ,  Klaus Keuerleber

发明人： Kai Weber ,  Christian Jacobi ,  Nico Gulden ,  Viresh Paruthi ,  Klaus Keuerleber

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by replacing the parts that cannot be formally verified easily. In one form the invention is applied to a logic design including a multiplier circuit. The multiplier is replaced (51) by pseudo inputs. The input signal values of the multiplier circuit are determined (54) automatically from a counterexample (53) delivered (52) by a functional formal verification system for a modified design where the multiplier is replaced by pseudo signals. The input signal values are combined (55) with other known inputs to form a test case (56) file that can be used by a logic simulator to analyse the counterexample (52) on the unmodified hardware design including the multiplier.

公开(公告)号：US07890903B2

公开(公告)日：2011-02-15

申请号：US12129127

申请日：2008-05-29

申请人： Kai Weber ,  Matthias Pflanz ,  Christian Jacobi ,  Udo Krautz

发明人： Kai Weber ,  Matthias Pflanz ,  Christian Jacobi ,  Udo Krautz

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A new and convenient methodology for proving the correctness of multiplier and multiply-accumulate circuit designs in a full custom design flow. Such an approach utilizes a basic description of the implemented algorithm, which is created in early phases of the design flow and requires only little extra work for the designer who spends most of the time in full-custom optimizations. Such an approach also defines arithmetic circuit at the arithmetic bit level and allows for the generation of a gate level netlist. Given a structural similarity between the specification and design under verification, a large amount of structural similarity between the generated netlists is obtained so that a standard equivalence checker can be utilized to verify the design against the specification.

摘要翻译： 一种新的便捷的方法，用于在完整的定制设计流程中证明乘法器的正确性和乘法积累电路设计。 这种方法利用了实现的算法的基本描述，该算法是在设计流程的早期阶段创建的，并且只需要花费大部分时间进行全自定义优化的设计人员的额外工作。 这种方法还在算术位电平处定义运算电路，并允许生成门级网表。 给定了在规范和验证设计之间的结构相似性，获得了生成的网表之间大量的结构相似性，从而可以利用标准的等价检验器来验证与规范相关的设计。

公开(公告)号：US20090300560A1

公开(公告)日：2009-12-03

申请号：US12129127

申请日：2008-05-29

申请人： Kai Weber ,  Matthias Pflanz ,  Christian Jacobi ,  Udo Krautz

发明人： Kai Weber ,  Matthias Pflanz ,  Christian Jacobi ,  Udo Krautz

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A new and convenient methodology for proving the correctness of multiplier and multiply-accumulate circuit designs in a full custom design flow. Such an approach utilizes a basic description of the implemented algorithm, which is created in early phases of the design flow and requires only little extra work for the designer who spends most of the time in full-custom optimizations. Such an approach also defines arithmetic circuit at the arithmetic bit level and allows for the generation of a gate level netlist. Given a structural similarity between the specification and design under verification, a large amount of structural similarity between the generated netlists is obtained so that a standard equivalence checker can be utilized to verify the design against the specification.

摘要翻译： 一种新的便捷的方法，用于在完整的定制设计流程中证明乘法器的正确性和乘法积累电路设计。 这种方法利用了实现的算法的基本描述，该算法是在设计流程的早期阶段创建的，并且只需要花费大部分时间进行全自定义优化的设计人员的额外工作。 这种方法还在算术位电平处定义运算电路，并允许生成门级网表。 给定了在规范和验证设计之间的结构相似性，获得了生成的网表之间大量的结构相似性，从而可以利用标准的等价检验器来验证与规范相关的设计。

公开(公告)号：US08600724B2

公开(公告)日：2013-12-03

申请号：US13552634

申请日：2012-07-18

申请人： Stefan Letz ,  Kai Weber ,  Juergen Vielfort

发明人： Stefan Letz ,  Kai Weber ,  Juergen Vielfort

IPC分类号： G06F17/50

CPC分类号： G06F9/3859 ,  G06F17/5022 ,  G06F2217/68

摘要： An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein the maintained information includes a determination of an execution length of a completely executed instruction, matching the maintained information about the completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.

摘要翻译： 公开了一种使用仿真环境中的处理器仿真模型验证处理器设计的改进方法，其中所述处理器仿真模型包括用于执行测试文件的至少一个指令的至少一个执行单元。 该方法包括跟踪每个执行至少一个指令中的每一个，监视每个模拟周期中的相关信号，维护关于至少一个指令的执行的信息，其中维护的信息包括完全执行的执行长度的确定 指令，将关于完全执行的指令的维护信息与由用户通过陷阱文件提供的一组陷阱元素相匹配，并且响应于在维护信息之间找到的匹配而将关于完全执行的指令的维护信息收集在监视文件中 和至少一个捕获元件。

公开(公告)号：US20090063829A1

公开(公告)日：2009-03-05

申请号：US12182211

申请日：2008-07-30

申请人： Stefan Letz ,  Kai Weber ,  Juergen Vielfort

发明人： Stefan Letz ,  Kai Weber ,  Juergen Vielfort

IPC分类号： G06F9/30

CPC分类号： G06F9/3859 ,  G06F17/5022 ,  G06F2217/68

摘要： An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model comprises at least one execution unit for executing at least one instruction of a test file. The method comprises tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein said maintained information comprises a determination of an execution length of a completely executed instruction, matching said maintained information about said completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.

摘要翻译： 公开了一种使用仿真环境中的处理器仿真模型验证处理器设计的改进方法，其中所述处理器仿真模型包括用于执行测试文件的至少一个指令的至少一个执行单元。 该方法包括跟踪每个执行至少一个指令中的每一个，监视每个模拟周期中的相关信号，维护关于至少一个指令的执行的信息，其中所述维护的信息包括确定完全执行的执行长度 指令，将关于所述完全执行的指令的所述维护信息与由用户通过陷阱文件提供的一组陷阱元素进行匹配，以及响应于在所述维护信息之间找到的匹配而将关于完全执行的指令的维护信息收集在监视文件中 和至少一个捕获元件。