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23 条记录 (耗时 0.014 秒)

    Network switch including bandwidth allocation controller
    6.
    发明授权
    Network switch including bandwidth allocation controller 失效
    网络交换机包括带宽分配控制器

    公开(公告)号：US06680908B1

    公开(公告)日：2004-01-20

    申请号：US09416939

    申请日：1999-10-13

    申请人： Patrick Gibson ,  Kam Choi ,  Christopher Hay ,  Gareth E Allwright

    发明人： Patrick Gibson ,  Kam Choi ,  Christopher Hay ,  Gareth E Allwright

    IPC分类号： G08C1500

    CPC分类号： H04L47/10 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/32 ,  H04L49/205 ,  H04L49/3027 ,  H04L49/351

    摘要： A network switch includes a plurality of receive ports for receiving addressed data packets and a plurality of transmit ports for forwarding the addressed data packets and structure responsive to data in said the packets for directing received packets to the transmit ports. In respect of at least one of the transmit ports the switch includes an output buffer for storing data packets before they are forwarded from the port and an allocation controller. The allocation controller allocates each packet destined for the buffer and each packet leaving the buffer for the port into at least one of a plurality of categories, which may be based on priority or protocol data and may define traffic types such as video or audio. For each of the categories there is an allocation register for defining a respective selected proportion of the memory space of the output buffer and structure for accumulating a running total of packet sizes, the total being reduced by the size of each packet in the respective category and leaving the buffer for the port. A packet is discarded when the running total of packet sizes for packets of the same category exceeds the respective proportion of the memory space defined in the respective allocation register. The organization of the switch allows the allocation of a minimum bandwidth for each of the categories.

    摘要翻译： 网络交换机包括用于接收寻址数据分组的多个接收端口和用于响应于所述分组中的数据转发所寻址的数据分组和结构的多个发送端口，用于将接收的分组引导到发送端口。 关于发送端口中的至少一个，交换机包括用于在从端口转发它们之前存储数据分组的输出缓冲器和分配控制器。 分配控制器分配目的地为缓冲区的每个分组和离开该端口的缓冲区的每个分组到多个类别中的至少一个，其可以基于优先级或协议数据，并且可以定义诸如视频或音频的业务类型。 对于每个类别，存在用于定义输出缓冲器的存储器空间的相应选择比例的分配寄存器和用于累积运行的分组大小的总和的结构，总共减少相应类别中的每个分组的大小， 为该端口留下缓冲区。 当相同类别的分组的分组大小的运行总计超过在相应分配寄存器中定义的存储器空间的相应比例时，丢弃分组。 交换机的组织允许为每个类别分配最小带宽。

    Water-supplying cleaning head
    9.
    发明申请
    Water-supplying cleaning head 失效
    供水清洁头

    公开(公告)号：US20060018705A1

    公开(公告)日：2006-01-26

    申请号：US10894960

    申请日：2004-07-20

    申请人： Christopher Hay

    发明人： Christopher Hay

    IPC分类号： A47L1/06 ,  A46B11/04

    CPC分类号： A47L13/26 ,  A46B11/06

    摘要： A water-supplying cleaning head has a block (4) carrying a cleaning means such as bristles or an abrasive surface on the underside thereof, a threaded coupling (6) for connecting a water-supplying handle thereto and with an internal water-supplying bore defined from the coupling (6) to the underside of the block (4), a resilient connecting neck portion (10) provided between the block (4) and coupling (61) allowing limited relative movement therebetween.

    摘要翻译： 供水清洁头具有在其下侧承载诸如刷毛或研磨表面的清洁装置的块体（4），用于将供水手柄连接到其上的螺纹联接件（6）和内部供水孔 从所述联接器（6）限定到所述块（4）的下侧，设置在所述块（4）和联接器（61）之间的弹性连接颈部（10）允许它们之间的有限的相对运动。

    Application specific integrated circuit with dual-mode system for externally accessible data buses and visibility buses
    10.
    发明授权
    Application specific integrated circuit with dual-mode system for externally accessible data buses and visibility buses 失效
    具有双模系统的专用集成电路，用于外部可访问的数据总线和可见性总线

    公开(公告)号：US06625684B1

    公开(公告)日：2003-09-23

    申请号：US09668301

    申请日：2000-09-25

    申请人： Fergus Casey ,  Vincent Gavin ,  Gareth E Allwright ,  Kam Choi ,  Christopher Hay ,  Kevin Loughran ,  Patrick Gibson

    发明人： Fergus Casey ,  Vincent Gavin ,  Gareth E Allwright ,  Kam Choi ,  Christopher Hay ,  Kevin Loughran ,  Patrick Gibson

    IPC分类号： G06F1300

    CPC分类号： G06F11/267 ,  G01R31/318505

    摘要： An application specific integrated circuit includes a multiplicity of operational blocks each of which includes at least one respective data bus and at least one respective visibility bus and a respective addressable multiplexer for selecting between those buses to provide an output on a to respective block bus. An interface block includes a first addressable multiplexer for selecting output data from a selected one of the blocks and providing an output; a register coupled to the output of the first addressable multiplexer; and a second addressable multiplexer for selecting between data provided by the output of the first addressable multiplexer and data in the register. Different portions of externally supplied address words are applied to the first addressable multiplexer and the respective addressable multiplexer, and a decoder is responsive to the address words for controlling the second addressable multiplexer. The arrangement provides a common multiplexing system for data buses and visibility buses.

    摘要翻译： 专用集成电路包括多个操作块，每个操作块包括至少一个相应的数据总线和至少一个相应的可见性总线和相应的可寻址复用器，用于在这些总线之间选择以在相应的模块总线上提供输出。 接口块包括第一可寻址复用器，用于从所选择的一个块中选择输出数据并提供输出; 耦合到第一可寻址复用器的输出的寄存器; 以及第二可寻址复用器，用于在由第一可寻址多路复用器的输出提供的数据和寄存器中的数据之间进行选择。 外部提供的地址字的不同部分被应用于第一可寻址复用器和相应的可寻址复用器，并且解码器响应于地址字来控制第二可寻址多路复用器。 该装置为数据总线和可视化总线提供了一个共同的多路复用系统。